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Power Minimization with Input Comparators in PLAs

IP.com Disclosure Number: IPCOM000112325D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Bechade, R: AUTHOR [+4]

Abstract

A power reducing technique for PLAs is described which latches the last previous data input so that it can be compared with the present data input to determine whether or not the PLA needs to be reevaluated. If the present input differs from the last previous input, the PLA operates in its normal mode. If the present input is identical to the last previous input, no PLA reevaluation is required, the previously latched output is used again, and no power dissipating data transitions occur within the PLA.

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Power Minimization with Input Comparators in PLAs

      A power reducing technique for PLAs is described which latches
the last previous data input so that it can be compared with the
present data input to determine whether or not the PLA needs to be
reevaluated.  If the present input differs from the last previous
input, the PLA operates in its normal mode.  If the present input is
identical to the last previous input, no PLA reevaluation is
required, the previously latched output is used again, and no power
dissipating data transitions occur within the PLA.

      The Figure shows a generic PLA design combined with the power
minimization circuit.  The power minimization circuit includes a
Delay Control Latch, a Detection Circuit (XOR), and a Detect
Generator.  The Delay Control Latch captures the data from the last
previous clock cycle.  The Detection Circuit is an XOR that compares
the present input data with the last previous input that is stored at
the Delay Control Latch output.  The XOR output is a logical 0 if two
consecutive inputs are different, but is a logical 1 if two
consecutive inputs are identifal.  Multiple XOR outputs derived from
multiple inputs are combined in the Detect Generator.  If any of the
multiple inputs change state from one clock cycle to the next, a
DETECT signal is not generated.  If none of the multiple inputs
change from one clock cycle to the next, a circuit-wide DETECT signal
is generated, and PLA evaluation is inhibited...