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Browse Prior Art Database

Checking Algorithm for Two Byte RAM with One or Two Byte Access

IP.com Disclosure Number: IPCOM000112327D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 106K

Publishing Venue

IBM

Related People

Bergey, AL: AUTHOR

Abstract

The invention is a checking algorithm for a two byte wide RAM memory that can be accessed (read or written) either one or two bytes at a time. The invention achieves a higher detection of multiple bit failures than the prior art.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Checking Algorithm for Two Byte RAM with One or Two Byte Access

      The invention is a checking algorithm for a two byte wide RAM
memory that can be accessed (read or written) either one or two bytes
at a time.  The invention achieves a higher detection of multiple bit
failures than the prior art.

      The problem solved by this invention is how to achieve high
failure detection in a two byte wide RAM memory buffer with byte wide
access.

      The buffer is a two-byte-wide RAM memory.  Access (reads and
writes) to the memory may occur to the left byte or the right byte or
to both bytes simultaneously.  The reliability requirements are:

1.  Must detect 100% of RAM module failures.

2.  Must detect 100% of single wire failures in data or address lines
    to or from the RAM modules.

3.  Must detect as many as possible multiple failures in data or
    address lines to or from the RAM modules.

The ability to access either bytes or byte-pairs is required.

      Solution - The invention uses seven RAM modules, as shown in
Fig. 1.  It provides 100% detection of single RAM module failures and
100% detection of single data or address signal failures.  By novel
use of the check bits, it achieves higher detection of multiple
address signal failures than the prior art.

      The invention, shown in Fig. 1, is constructed of 4-bit-wide
RAM modules.  In order to support 100% detection of any failure in a
single 4-bit-wide RAM module, 4 check bits are required.  Thus, the
simplest possible checking algorithm for a two byte wide buffer with
100% detection of any RAM module failure would use four modules for
the data, and one module for checking.  However, locating all the
check information in a single module complicates single byte writes,
as the resulting check nybble must contain information both from the
byte that was written and the byte that was not changed.  This
invention handles the problem of single byte writes to a two byte
wide memory by using two RAM modules for check information, one
devoted to the right byte, and the other module devoted to the left
byte.

      Thus seven RAM modules are required.  Two 4-byte-wide RAM
modules handle the left data byte, one handles the left check byte,
two handle the right data byte, one handles the right check byte, and
one RAM module is reserved for a spare.

      The algor...