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High Resolution Digital Phase-Locked Logic Circuit

IP.com Disclosure Number: IPCOM000112328D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 104K

Publishing Venue

IBM

Related People

Kelley, PE: AUTHOR [+3]

Abstract

Digital Phase-Locked Logic (DPLL) typically has a finite recovered clock resolution. This clock phase granularity is usually determined by the number of taps in the delay line, gate delays, multiplexer skews, etc. For this reason, the analog PLLs are often chosen in the applications that require a high degree accuracy. The proposed DPLL circuit solves the problem of the clock phase resolution.

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High Resolution Digital Phase-Locked Logic Circuit

      Digital Phase-Locked Logic (DPLL) typically has a finite
recovered clock resolution.  This clock phase granularity is usually
determined by the number of taps in the delay line, gate delays,
multiplexer skews, etc.  For this reason, the analog PLLs are often
chosen in the applications that require a high degree accuracy.  The
proposed DPLL circuit solves the problem of the clock phase
resolution.

      Digital Phase-Locked Logic (DPLL) is a critical part of LANs
and other communication systems.  The DPLL performs clock recovery.
It also eliminates the data jitter through data regeneration.  DPLL's
are also used in the magnetic data storage systems.  In both magnetic
disc and tape storage applications, the DPLL performs a read channel
data clock recovery.

      Fig. 1 shows a block diagram of the DPLL.  It consists of a
Variable Delay Line, a Multiple Tap Delay Line, a Data Edge Sorting
Circuit, the Histogram counters, a Data Regeneration circuit and a
DPLL Algorithm.

      A local clock is applied to an input of the Variable Delay
Line.  The Variable Delay Line is adjusted by the DPLL Algorithm so
as to maintain the recovered clock in the center of the eye diagram.
The recovered clock is taken from the center tap of the Multiple Tap
Delay Line.

      Operation is achieved by feeding the output of the Variable
Delay Line to the Multiple Tap Delay Line.  The Multiple Tap Delay
Line generates a plurality of clocks with the same frequency, but
different phases.  These plurality of clocks and data are provided to
the inputs of the Data Edge Sorting circuit.  The Data Edge Sorting
circuit measures the incoming data edge phase in reference to the
clock phase applied to the Multiple Tap Delay Line.  It also sorts
the data edges into the time slots determined by the plurality of the
clocks generated by the Multiple Tap Delay Line.  The data edge sorts
are provided to the Histogram Counters for storage and accumulation.
A sample of the sorts stored in the Histogram Counters constitutes a
histogram (Fig. 2).  This histogram is a digitized version of the
communication link eye pattern.  It is desirable to achi...