Browse Prior Art Database

Processor Bus Clocking Speed Control

IP.com Disclosure Number: IPCOM000112342D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Moore, CR: AUTHOR [+3]

Abstract

Disclosed is a method of clocking a microprocessor bus at any integral multiple of the microprocessor's internal clocking speed, thereby allowing the microprocessor's external bus to run at a slower speed than the microprocessor's internal logic.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 93% of the total text.

Processor Bus Clocking Speed Control

      Disclosed is a method of clocking a microprocessor bus at any
integral multiple of the microprocessor's internal clocking speed,
thereby allowing the microprocessor's external bus to run at a slower
speed than the microprocessor's internal logic.

      Slowing the internal clock of a processor to the maximum speed
that the processor's bus system can handle severely limits overall
processor system performance.  It is therefore desirable to operate
the processor external bus at some fraction of the processors
internal clock.

      The Figure shows how this is accomplished using a two inputs to
the processor: a processor clock (PROC CLOCK) and a BUS_PHASE_ signal
to control the start of the external bus cycle.

      As shown in the Figure, the rising edge of PROC CLOCK
determines the start of the processor's internal state transitions.
The rising edge is also used to sample the state of the BUS_PHASE_
input.  When the sampled BUS_PHASE_ input is asserted (LOW), the
external bus transitions will start.

      This method allows the bus to operate at any integral multiple
slower than the processor's internal clock speed.  By controlling the
duty cycle of the BUS_PHASE_ input, the processor can work at full
speed (asserting BUS_PHASE_ continuously), half speed (one cycle
asserted, one cycle negated), one-third speed (one cycle asserted,
two cycles negated, as shown in the figure), and so forth.

      This B...