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Browse Prior Art Database

Peripheral Component Interconnect Daughter Card Arbitration

IP.com Disclosure Number: IPCOM000112345D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 3 page(s) / 124K

Publishing Venue

IBM

Related People

Nasiff, A: AUTHOR [+3]

Abstract

Disclosed is a means for controlling the arbitration between a daughter card and an I/O controller circuit to which the daughter card is connected, even when the daughter card and the I/O controller circuit have different priorities.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Peripheral Component Interconnect Daughter Card Arbitration

      Disclosed is a means for controlling the arbitration between a
daughter card and an I/O controller circuit to which the daughter
card is connected, even when the daughter card and the I/O controller
circuit have different priorities.

      As shown in Fig. 1, a number of attachment cards (10) are
connected to a Micro Channel* bus (12) extending from a system
processor (14).  Some or all of the attachment cards (10) include a
daughter card (16) attached to a local Peripheral Component
Interconnect (PCI) bus (18), which is in turn interconnected with the
Micro Channel bus (12) through an I/O controller circuit (20).
Daughter card (16) may alternately be attached to a planar, or system
board (not shown) including graphics adapter circuits and providing
the PCI bus.

      There may be two devices on each attachment card competing for
control of the Micro Channel--the daughter card (16) and the I/O
controller circuit (20).  The daughter card and the I/O controller
circuit may have the same need for access to the Micro Channel, and
hence the same arbitration level.  Alternately, the I/O controller
circuit may have a higher-priority require- ment than the daughter
card, or the daughter card may have a higher-priority requirement
than the I/O controller circuit.

      The configuration process associated with each daughter card
(16) includes writing information to a daughter card PCI Bridge
Enable Register, as shown in Fig. 2.  In this register, Bit 1 is a
read only placement bit, set at zero if I/O controller circuit (20)
is attached directly to the system board, and at one if this I/O
controller circuit is attached to an attachment card (10) as shown in
Fig. 1.  The Arbitration Level Bits, Bit 3 and Bit 4, are used only
when I/O controller circuit (20) is on an attachment card (10).

      Each adapter card 10 has only one priority level on the Micro
Channel bus (12), which is determined by Bits 3 through 6 of the
register shown in Fig. 2.  Two Arbitration Level Bits, Bits 3 and 4,
are used to handle the various possibilities described above for
relative priority between the daughter card (16) and the I/O
controller circuit.  The locking out of a lower-priority function by
Micro Channel traffic is also prevented.  A lower priority device may
only arbitrate on the bus if a higher priority device is "not"
requesting usage of the Micro Channel.  To ensure that another
device, having a yet lower priority,  does not lock out the
lower-p...