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Dram Page-Mode to Perform Read-Modify-Write

IP.com Disclosure Number: IPCOM000112355D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Ackerman, JE: AUTHOR

Abstract

A read-modify-write operation for an Error Checking/Correction (ECC) system is provided by using the page-mode of a Dynamic Random Access Memory (DRAM) rather than a signal from an Output Enable (OE) pin.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Dram Page-Mode to Perform Read-Modify-Write

      A read-modify-write operation for an Error Checking/Correction
(ECC) system is provided by using the page-mode of a Dynamic Random
Access Memory (DRAM) rather than a signal from an Output Enable (OE)
pin.

      In ECC memory systems, if less than a full word of memory needs
to be written, i.e., a byte written to a 32-bit wide memory, a
read-modify-write is performed.  For memories with common
Input/Output (I/O) data pins, the output enable pin is normally used
for this function.  For a memory controller implemented in an I/O
limited package, this extra pin can be very costly.

      Typical memory controllers interface to a 40-bit wide, with
only 39-bits being used, memory made up of ten four-bit chips.  Of
these bits, 32 are used for data and seven for the ECC codes, or
check bits.  If less than a 32-bit word of data, i.e., a byte, is
written in a location, then the following sequence occurs:

1.  A 32-bit data word and seven associated check bits are read and
    latched externally, with the data word being corrected if
    necessary.

2.  The byte to be written is inserted into the 32-bit data word and
    new check bits are generated.

3.  The 32-bit data word, with the new byte, and the new check bits
    are written back to the memory.

      A standard timing diagram for this procedure is shown in Fig.
1.  This diagram indicates a read, with OE driven low, followed by a
late write, with write driven low.

      The diagram in Fig. 2 illustrates the pulse timing of the
read-...