Browse Prior Art Database

Multiple Channel Data Descriptor Prefetch Mechanism

IP.com Disclosure Number: IPCOM000112360D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Johnson, SH: AUTHOR

Abstract

Disclosed is a method for limiting the number of Peripheral Component Interconnect (PCI) bus arbitration cycles for a PCI Streamer family adapter when fetching transmit and receive descriptors. Streamer family adapters rely on data descriptors in host storage, built by device drivers, for defining the locations and sizes of the data space available to the transmit and receive channels.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Multiple Channel Data Descriptor Prefetch Mechanism

      Disclosed is a method for limiting the number of Peripheral
Component Interconnect (PCI) bus arbitration cycles for a PCI
Streamer family adapter when fetching transmit and receive
descriptors.  Streamer family adapters rely on data descriptors in
host storage, built by device drivers, for defining the locations and
sizes of the data space available to the transmit and receive
channels.

      Streamer family adapters are equipped with two transmit
channels and one receive channel.  The prefetch mechanism is designed
to buffer data for each channel, based on a foreknowledge of the
number of four-byte words that will be required by each channel for
proper operation.

The receive channel follows the following pattern when accessing its
data descriptor:

1.  Fetch Data Buffer Pointer field (offset 8)

2.  Fetch Data Buffer Length field (offset C)

3.  Store Frame Data

4.  Fetch Forward Pointer field (offset 0)

5.  Store Data Buffer Length field (offset C) if EOF

6.  Store Status field (offset 4)

      The first two fetches are grouped together by the prefetch
mechanism.  The Data Buffer Pointer is sent on to the busmaster
control logic, while the Data Buffer Length is stored in the prefetch
buffer.  When the busmaster control logic then requests the Data
Buffer Length it is retrieved from the prefetch buffer, avoiding a
PCI bus arbitration cycle.  For the receive channel, the prefetch
mechanism saves one out of three PCI Bus arbitrations for descriptor...