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Browse Prior Art Database

Packaging Concept Providing Parallel Substrate Build for C4 Modules

IP.com Disclosure Number: IPCOM000112374D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Hoefer, DE: AUTHOR [+2]

Abstract

Disclosed is a process that allows a C4 module to be manufactured using two subassemblies; one pin carrier and one chip carrier. The chip carrier is attached to the pin carrier using a reflow solder process similar to that used for chip attachment.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Packaging Concept Providing Parallel Substrate Build for C4 Modules

      Disclosed is a process that allows a C4 module to be
manufactured using two subassemblies; one pin carrier and one chip
carrier.  The chip carrier is attached to the pin carrier using a
reflow solder process similar to that used for chip attachment.

      The chip carrier is manufactured in a similar manner as a flat
pack package, except that the I/O connections are located in a grid
format in the interior of the carrier, similar to the pin connection
pads on a pin grid array.  The chip carrier may be made of many
materials, including ceramic, molybdenum, silicon, or polymers.

      The pin carrier interposer holds an array of pins that matches
the grid pattern on the chip carrier.  The pin carrier interposer is
attached to the chip carrier through a solder reflow process.  Upon
completion, the chip is protected between the chip carrier and the
pin carrier.  A heat sink may be molded or designed in the pin
carrier to facilitate cooling of the chip (Figure).