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Single-Bit Correct, Double-Bit Detect Error Checking/Correction Scheme

IP.com Disclosure Number: IPCOM000112383D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 105K

Publishing Venue

IBM

Related People

Ackerman, JE: AUTHOR

Abstract

A logical scheme is provided for detecting and correcting single-bit errors and for detecting multi-bit errors relative to data stored in a dynamic random access memory. The data is stored in 32-bit groups with seven check bits stored for each group. The check bits are generated by an exclusive-NOR (XNOR) circuit arranged in a tree pattern which is 16-bits wide maximum. On readout, data bits and an associated check bit are passed through an exclusive-OR (XOR) tree to produce seven syndrome code bits. These bits identify single-bit errors, multi-bit errors and no error. The syndrome code bits can then be used to correct single-bit errors. Also, three- and four-bit errors in a four-bit wide chip are detectable as a chip-kill-detect, and gross error of all 1's, or all 0's, is detectable.

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Single-Bit Correct, Double-Bit Detect Error Checking/Correction Scheme

      A logical scheme is provided for detecting and correcting
single-bit errors and for detecting multi-bit errors relative to data
stored in a dynamic random access memory.  The data is stored in
32-bit groups with seven check bits stored for each group.  The check
bits are generated by an exclusive-NOR (XNOR) circuit arranged in a
tree pattern which is 16-bits wide maximum.  On readout, data bits
and an associated check bit are passed through an exclusive-OR (XOR)
tree to produce seven syndrome code bits.  These bits identify
single-bit errors, multi-bit errors and no error.  The syndrome code
bits can then be used to correct single-bit errors.  Also, three- and
four-bit errors in a four-bit wide chip are detectable as a
chip-kill-detect, and gross error of all 1's, or all 0's, is
detectable.

      With an ever increasing amount of dynamic random access memory
used in systems, errors, both hard and soft, are also increasing,
while higher quality and reliability are being demanded by users of
these systems.  Thus, Error Checking/Correction (ECC) systems are
being required in high-end systems down to desktop systems.  The
price-sensitive systems require an ECC scheme that offers maximum
performance at minimum cost.

      As indicated in Fig. 1, the system includes a memory control
chip 10 and a series of ten memory blocks 12, with each memory block,
or chip, being4-bits wide and being connected to the memory control
chip 10 by data lines D and check bit lines cb.  The memory control
chip 10 feeds RAS, CAS and address signals to each of the blocks of
the series of blocks 12 through lines 14.

      Check bits cb are produced by applying predetermined data bits,
as identified in Fig. 2, to the inputs of an XNOR tree, indicated in
Fig. 3.  It can be seen that when the data bit inputs identified in
Fig. 3, and also in the top row of X's of Fig. 2, are applied to the
inputs of the XNOR tree, a check  bit 6, cb6, is produced at the
output of the XNOR tree.  It should be noted from Fig. 2 that the
different check bits cb are produced by applying a different series
of data bits to the input of the XNOR tree of Fig. 3.

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