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Multiprocessor Interrupts for Microprocessors Using Processor ID Based Vectoring

IP.com Disclosure Number: IPCOM000112395D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 157K

Publishing Venue

IBM

Related People

Karim, F: AUTHOR [+4]

Abstract

Interrupt handling procedures for multiprocessors are often costly and complicated. A method is disclosed that requires fewer on-chip registers than the standard method and has the same performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 42% of the total text.

Multiprocessor Interrupts for Microprocessors Using Processor ID
Based Vectoring

      Interrupt handling procedures for multiprocessors are often
costly and complicated.  A method is disclosed that requires fewer
on-chip registers than the standard method and has the same
performance.

      UNIPROCESSOR INTERRUPTS - On a uniprocessor system, interrupt
handling is straightforward.  Fig. 1 illustrates the basic process.
When an interrupt occurs, the processor saves the current Program
Counter (PC), determines the vector table line address, and branches
to the proper interrupt handler.

      The interrupt handler saves the condition codes and registers
it will use to system memory, does the work the interrupt requires,
restores the state, resets its interrupt request flag, and branches
back to the saved PC+1.

      MULTIPROCESSOR INTERRUPTS - On a multiprocessor machine using
shared memory, interrupts are more complicated.  Suppose processor 1
has an interrupt.  It saves its registers and proceeds to handle the
interrupt.  While this is happening, processor 2 may have an
interrupt.  Without special precautions, processor 2 would save its
registers into the same memory location that processor 1 used.

      THE STANDARD SOLUTION - A standard solution to this problem is
to use two registers, the Temporary Save Register (TSR) and the Data
Address Save Register (DASR).  The DASR in each processor must be
initialized to hold an address unique to that specific processor.
When an interrupt occurs, the PC is saved, the address of the
interrupt handler is determined as above, and a branch is IND$FILE
PUT ATEA1237 TIFF A

      The interrupt handlers are common code accessible to each
processor.  In each interrupt handler, the contents of R0 (a general
purpose register) are saved into the TSR, and R0 is loaded with the
DASR value.  Now the registers are saved into the address specified
by R0 (the DASR value).  Since this address is different for each
processor, no overwriting will occur.  This process is shown in Fig.
2.

      This method works adequately, but requires two additional
registers per processor.  A method is desired that has the same
performance, but eliminates the need for these extra registers.

      THE SOLUTION DISCLOSED - The solution disclosed eliminates the
need for the TSR and DASR registers.  It saves two 32-bit registers
per processor, a significant amount on a microprocessor.  It has the
same performance, in terms of overhead instructions needed for each
interrupt.  The only drawback is that it consumes a slightly larger
amount of system memory.  However, the amount it needs is very small
compared to the size of system memory.

      A certain number of bits are reserved in the MSR (machine state
register) to indicate processor ID.  The log base 2 of the maximum
number of processors gives the number of bits needed.  For example,
if up to 64 microprocessors can be linked,...