Browse Prior Art Database

Low-Cost Error Handling Implementation

IP.com Disclosure Number: IPCOM000112399D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

East, RE: AUTHOR [+3]

Abstract

Disclosed is one design point for minimizing the silicon chip die area used in error handling in one microprocessor implementation of the IBM RS/6000* system architecture. This particular problem included melding of different sources of errors into something that was manageable and reasonable in silicon chip die area to implement and eliminating the need for an external support processor used by the more costly implementations to implement these functions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 74% of the total text.

Low-Cost Error Handling Implementation

      Disclosed is one design point for minimizing the silicon chip
die area used in error handling in one microprocessor implementation
of the IBM RS/6000* system architecture.  This particular problem
included melding of different sources of errors into something that
was manageable and reasonable in silicon chip die area to implement
and eliminating the need for an external support processor used by
the more costly implementations to implement these functions.

      This microprocessor implementation had errors either stemming
from combinatorial detection logic or from microcode detecting an
error (from an on-chip co-processor).  The co-processor ran
continuously and performed several dozen functions (such as I/O,
virtual translation table walks, real time clock, DMA transfers) in
parallel with the main processing units and in doing so, had to
handle errors that it detected.  All errors from either source where
required to be posted to NVRAM, which only the co-processor had
access to.  In addition, the reset panel button when depressed takes
on different meanings (hardware reset, software reset, or display
first/next LED code) based on values in the NVRAM, again which only
the co-processor had access to.  Dual access to the NVRAM was not a
viable option in this design point.

      To resolve all this, the hardware error codes and the reset
panel button signal were feed into the on-chip co-processor to
interrupt th...