Browse Prior Art Database

Asynchronous Signal Tracking Logic

IP.com Disclosure Number: IPCOM000112410D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 128K

Publishing Venue

IBM

Related People

Bronson, T: AUTHOR [+3]

Abstract

This disclosure describes the means to stretch the use of older technologies or extend the abilities of new technologies in the area of interface synchronization.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Asynchronous Signal Tracking Logic

      This disclosure describes the means to stretch the use of older
technologies or extend the abilities of new technologies in the area
of interface synchronization.

      As asynchronous interfaces increase in speed, the clock rate
needed to synchronize to the interface can exceed the viable clock
rate for a given technology.

      Asynchronous interfaces require synchronization to the
interface chip's native clocks in order to control the flow of data
through the chip.  In order to recreate a signal Nyquist criterion
requires that it must be sampled at at least twice the frequency of
the highest frequency contained in the signal.  In a strictly digital
application the component frequencies making up the transition edges
do not need to be considered in determining the sampling rate.

      Theoretically fs > = 2fa, where fs is the sampling frequency
and fa is the maximum asynchronous signal frequency.  If sampling is
exactly twice the asynchronous frequency violation of the set or hold
time of the sampling latch can cause metastability and aliasing.
Therefore fs > 2fa + k, where k is some technology dependent constant
based on the setup and hold time of the sampling latch.

      This invention is hardware to create an effective fa (fe) which
is much lower than the actual fa, fe = fa/d.  d is a divide constant
used to lower fa so that fs > 2fe + k, or fs > 2 (fa/d) + k.

      Fig.  1 is a high level diagram of the synchronization
circuitry.  The Signal Conditioning block repowers the asynchronous
signal and provides the clock signals used by the Divide By d block.
The Divide By d block is a modulo d counter.  The Decoder block
decodes the modulo d counter to enable the appropriate
Synchronization Stream block.  The Synchronization Stream block
synchronizes the effective asynchronous signal fe to the internal
clocks.

      Fig. 2 shows an IBM CMOS II LSSD implementation of the Signal
Conditioning block.  The clock splitter book provides the LSSD clocks
needed by the modulo 4 (gray code) counter in Fig. 3.  Fig. 4 shows
the simple AND logic used to decode the asynchronous counter.  The
asynchronous counter and decode logic could be replaced by a circular
shift register ring using the splitter book clocks.  With only one
shift register bit at a time active high extra decoding logic is not
needed.  (This implementation had additional functional requirements
not germane to the disclosure so the ring method was not...