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Browse Prior Art Database

Automatic Phase Adjustment

IP.com Disclosure Number: IPCOM000112420D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Sakakihara, M: AUTHOR [+2]

Abstract

In a system which provides a function of converting analog signals of Cathode Ray Tube (CRT) port (like PS/2 monitor interface) to digital signals and timings required for a digital display (like TFT/LCD panel), the system equips with Analog to Digital Converter (ADC) and Phase Lock Loop (PLL) to generate a sampling clock to sample the analog video signals at ADC. The analog video signals will shape dull (slow rising time) wave forms normally, because of fixes for ElectroMagnetic Interference (EMI). So if ADC samples the rising portion of the analog video signals, the values from ADC are not correct. So the PHASE (Sampling point of analog video signals) should be a saturated portion of the video signals to capture the correct value.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Automatic Phase Adjustment

      In a system which provides a function of converting analog
signals of Cathode Ray Tube (CRT) port (like PS/2 monitor interface)
to digital signals and timings required for a digital display (like
TFT/LCD panel), the system equips with Analog to Digital Converter
(ADC) and Phase Lock Loop (PLL) to generate a sampling clock to
sample the analog video signals at ADC.  The analog video signals
will shape dull (slow rising time) wave forms normally, because of
fixes for ElectroMagnetic Interference (EMI).  So if ADC samples the
rising portion of the analog video signals, the values from ADC are
not correct.  So the PHASE (Sampling point of analog video signals)
should be a saturated portion of the video signals to capture the
correct value.

      This article describes the method to adjust this phase
automatically and convert the analog signals to the digital
correctly.

      Figure shows the example of this method.  There are three key
portions in this Figure.  1st portion is to get Phase (#1 to #4), 2nd
portion is to shift Hsync (Horizontal Synchronous Pulse) for PLL (#6
to #7) and 3rd is to calculate how long to shift Hsync based on
detected Phase.

      1st portion consists of Converter #1, Delay line #2, D-FF
(D-flip-flop) #3 and Binary conversion circuit #4.  Converter #1 is
to convert the analog signal to the signal with enough level for
Delay line #2, and the turn-on voltage is set to a little above black
level to get the rising edge of the video signal.  Delay line #2 has
some pieces of delay chained sequentially and each delay has output
(tap).  In the Figure, number of delays is M.  "M" means the
resolution of the detect Phas...