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ROM Instruction Fetch and Instruction Cache Sync Implementations

IP.com Disclosure Number: IPCOM000112424D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

East, RE: AUTHOR [+2]

Abstract

Disclosed is a design method for minimizing the silicon chip die area used to implement the instruction fetching mechanism from Read-Only Memory (ROM) and the Instruction Cache Synchronization instruction (ICS) in the microprocessor used in the low-cost implementation of the RS/6000* system. In this design point, the Read-Only Memory was attached to the I/O channel, not the memory channel. The ICS instruction required purging all pre-fetched instructions and finishing execution of any instruction prior to it.

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ROM Instruction Fetch and Instruction Cache Sync Implementations

      Disclosed is a design method for minimizing the silicon chip
die area used to implement the instruction fetching mechanism from
Read-Only Memory (ROM) and the Instruction Cache Synchronization
instruction (ICS) in the microprocessor used in the low-cost
implementation of the RS/6000* system.  In this design point, the
Read-Only Memory was attached to the I/O channel, not the memory
channel.  The ICS instruction required purging all pre-fetched
instructions and finishing execution of any instruction prior to it.

      The effective address of the original RS/6000 microprocessors
was 32 bits.  Therefore, the instruction execution unit would
normally manipulate 32 bit values.  To save silicon chip die area,
the design manipulated 12 bit values, a value that corresponded to
the "page" size of the machine (the page size is the part of the
effective address that maps directly to the real address, i.e., it is
not affected in the virtual to real address translation process).
The upper 20 bits of the current real address was saved in a register
and appended appropriately.  For address manipulations that jumped
past a page boundary, the fixed point unit 32 bit adder was utilized.
If the instruction execution unit sequentially crossed the page
boundary, a dummy branch instruction to the next address location was
executed by the fixed point 32 bit adder to generate the next
address.

      The impl...