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Use of the SYNC Instruction to Synchronize Completion of Translation Look-aside Buffer Invalidate in a Multi-Processor System

IP.com Disclosure Number: IPCOM000112440D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Kaiser, JM: AUTHOR [+4]

Abstract

Disclosed is a hardware solution for synchronization of Translation Look-aside Buffer (TLB) shoot down in a Symmetric Multi-Processor System (SMP). By using the SYNC instruction in conjunction with the TLB Invalidate (TLBI) instruction, a method is described to ensure translation coherency among all processors that are contained within the SMP environment.

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This is the abbreviated version, containing approximately 80% of the total text.

Use of the SYNC Instruction to Synchronize Completion of Translation
Look-aside Buffer Invalidate in a Multi-Processor System

      Disclosed is a hardware solution for synchronization of
Translation Look-aside Buffer (TLB) shoot down in a Symmetric
Multi-Processor System (SMP).  By using the SYNC instruction in
conjunction with the TLB Invalidate (TLBI) instruction, a method is
described to ensure translation coherency among all processors that
are contained within the SMP environment.

      The TLBI instruction is broadcast from the sending processor to
all of the receiving processors.  At this time the sending processor
does not know whether each receiving processor has finished the TLB
invalidation process since the TLBI process may take a long and
varying times in each receiving processor.  The sending processor is
now required to broadcast a SYNC instruction after the TLBI
instruction, before proceeding, in order to ensure the receiving
processors have finished the TLBI process.  It is up to the each
receiving processors to hold off acknowledgement of the received sync
operation until the received TLBI operation has completed by that
processor.  Therefore, if all receiving processors have release the
hold of the sync operation, the sending processor is allows to
continue now knowing that the TLBI instruction has taken effect
throughout the SMP environment.

      Translation coherency is maintained by the sending processor
executing first the TLBI in...