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Browse Prior Art Database

High Speed High Density Comparator for VLSI Implementation

IP.com Disclosure Number: IPCOM000112445D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 82K

Publishing Venue

IBM

Related People

Wang, PZ: AUTHOR

Abstract

Disclosed is a circuit for high speed, high density data comparison. The novel idea is to use an unbalanced differential latch to retain a pre-defined logic state. The circuit uses a novel delay and output scheme to be immune to noise. The design is implemented in two stages to achieve a precharged, domino evaluate clocking scheme. (Fig. 1). The data comparison is accomplished in on clock cycle.

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High Speed High Density Comparator for VLSI Implementation

      Disclosed is a circuit for high speed, high density data
comparison.  The novel idea is to use an unbalanced differential
latch to retain a pre-defined logic state.  The circuit uses a novel
delay and output scheme to be immune to noise.  The design is
implemented in two stages to achieve a precharged, domino evaluate
clocking scheme.  (Fig. 1).  The data comparison is accomplished in
on clock cycle.

      As shown in Fig. 1, the 1st stage compares N pairs of input
data:  A1,A2,.....AN Vs B1,B2,.....BN which are always all low during
precharge.  SET is a precharge signal, When SET is low, both NODE1
and NODE2 are charged up to VDD.  When SET is high, the circuit is in
evaluation mode.

      Pass gates T10 and T11 form an XOR function, such that when A1
is not equal to B1, it generates a high signal which turns on devices
T8 and T9.  Hence, NODE1 and NODE2 will have a differential signal.
When A1 is equal to B1, T8 and T9 will be off.  Their outputs are
tristated.  Device T2 serves as an equalizer.

      During precharge, n-channel device T5 is off.  NODE1 and NODE2
are charged up to VDD.  Both OUT and OUTN are low.

      During evaluation, precharge devices T0, T1 and T2 are off.
Device T5 is turned on.  Since both NODE1 and NODE2 are precharged
high, devices T3 and T4 start to discharge NODE1 and NODE2.

      The circuit is designed such that the load capacitance of NODE1
is N times larger than load capacitance of NODE2....