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Designing for I/O Address Translation Tables with Minimal System Cost

IP.com Disclosure Number: IPCOM000112447D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

East, RE: AUTHOR [+2]

Abstract

Disclosed is a design method for minimizing the system cost for the IBM RS/6000* I/O address translation unit.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 89% of the total text.

Designing for I/O Address Translation Tables with Minimal System Cost

      Disclosed is a design method for minimizing the system cost for
the IBM RS/6000* I/O address translation unit.

      In some systems including the IBM RS/6000 systems, I/O
addresses are virtual, i.e., the address must be translated from one
form (virtual) to another (real).  Hardware tables, initialized by
software, are required.  For performance reasons, the initial IBM
RS/6000 systems placed these tables in separate Static Random Access
Memory (SRAM) instead of main system storage and logically close to
the I/O controller.

      To reduce the system cost associated with this architecture, a
design implemented the hardware translation tables in main system
storage.  A register in the microprocessor contained a pointer to the
start location of the hardware translation tables.  The software was
restricted to place the hardware translation tables on the same
address boundary as the size of the table itself.  For example, if
the hardware translation table was defined to be 64 Kbytes, then the
hardware translation table origin must be on a 64 Kbyte address
boundary.  Thus, the algorithm to generate the address into the
hardware translation table was easily calculated, logically 'OR' the
origin pointer with the offset of the I/O address.  A small hardware
translation table cache was maintained within the microprocessor thus
the performance degradation to access the translation tables...