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Forcing Errors in CEFS Simulation

IP.com Disclosure Number: IPCOM000112450D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Mickelson, KB: AUTHOR

Abstract

In Compiled Enhanced Functional Simulator (CEFS), an attribute dealt with involves the fact that only one source can drive a signal or latch element. For this reason special designs must be made to allow a signal which might be driven to a one to be driven to zero for error testing.

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Forcing Errors in CEFS Simulation

      In Compiled Enhanced Functional Simulator (CEFS), an attribute
dealt with involves the fact that only one source can drive a signal
or latch element.  For this reason special designs must be made to
allow a signal which might be driven to a one to be driven to zero
for error testing.

      In other words CEFS uses a dot OR to combine signals common to
a particular facility name.  A signal cannot be forced to a zero, if
one of the sources tied to it are a one.  This is particularly common
when trying to setup tests for error situations.

      The way around this is to add AND logic into a special term
which, when driven to a value will force a signal point or net to
zero.  The equations below allow this to be seen easily.  It is an
example from a real design behavioral used for testing.

     BIS_DPAREN3 = ^CF2_CMD & BIS_BAD_CYCLE_$ & BIS_DPAREN2

     BIS_DPAR_INVSL$ = BIS_DPAREN3 & BIS_DPAREN6

    CF2_DPAREN_$ = BIS_DPAR_INVFP & BIS_DPAR_INVSL$ & BIS_DPAREN7

     TRUTH TABLE

     -----------

     output         spec signal

     CF2_DPAREN_$    BIS_DPAREN2    BIS_DPAREN3  BIS_DPAR_INVSL$
           0              0               0              0
           term           1               term           term
           dependant                      depend...