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Separating the Interaction of Address and Data State during Bus Data Transfers

IP.com Disclosure Number: IPCOM000112465D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 102K

Publishing Venue

IBM

Related People

Allen, MS: AUTHOR [+6]

Abstract

For many applications, the performance of modern microprocessors can be governed by the ability to access data outside of the processor. As a result, many of today's microprocessors invest significant resources into the bus interface and control logic. One common tactic is to use separate buses for the address and data transfers. Another tactic is to allow pipelined accesses and split transactions to occur on these buses. These advancements cause additional design complexity in the bus interface logic.

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This is the abbreviated version, containing approximately 52% of the total text.

Separating the Interaction of Address and Data State during Bus Data
Transfers

      For many applications, the performance of modern
microprocessors can be governed by the ability to access data outside
of the processor.  As a result, many of today's microprocessors
invest significant resources into the bus interface and control
logic.  One common tactic is to use separate buses for the address
and data transfers.  Another tactic is to allow pipelined accesses
and split transactions to occur on these buses.  These advancements
cause additional design complexity in the bus interface logic.

      In addition to providing data access support for the local
processor, the bus interface must also support system level coherency
requirements.  In multiprocessor systems, the bus interface must
balance local processor performance with overall system bus
utilization.  As a result, the bus interface must support a wide
range of transaction types and the ability to correctly coordinate
coherency actions.  These requirements complicate the design even
further.

      Although previous bus interface designs have been constructed
that correctly balance these requirements, they tend to couple the
address bus operation with various aspects of the data bus operation.
This type of coupling makes the already complex design even worse.
This complexity has the effect of restricting future expandability of
the bus interface and increasing the risk of the overall design.

      The bus interface on the preferred microprocessor of the
present invention has been carefully designed to decouple the address
and data buses, yet still meet all of the requirements described
above.

      This invention allows a simple construction of the state
machines which control the address and data transfers on a
split-transaction bus.  It especially helps those buses which support
pipelined data transfers.  This simplification occurs by restricting
the external control of the address transfer and of the data transfer
in such a way that interactions between the transfers do not exist
thus allowing for separate (non-interacting) state control of the two
buses.

The following signals and restrictions comprise the solution:

      A single signal is used to terminate the address tenure (for
the preferred microprocessor, this signal is called AACK_).  This
termiation signal must be implemented and must be toggled for each
tenure (i.e., it cannot be tiedactive).  No data bus signals can
cause the address tenure to terminate.  Two status lines are sampled
the cycle following address termination (for the preferred
microprocessor, these signals are called ARTRY_ and SHD_).  The
address tenure c...