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High-Speed Memory Consistency Mechanism for Multiprocessors

IP.com Disclosure Number: IPCOM000112469D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 132K

Publishing Venue

IBM

Related People

Fukuda, M: AUTHOR [+3]

Abstract

Disclosed is a system to realize the release consistency [1] model efficiently.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 48% of the total text.

High-Speed Memory Consistency Mechanism for Multiprocessors

      Disclosed is a system to realize the release consistency [1]
model efficiently.

      To facilitate the description of event orderings, we present
formal definitions for the stages that a memory request goes through.
The following two definitions are from [2,3].  In the following, P(i)
refers to processor i.

      Definition 1: Performing a Memory Request A LOAD by P(i) is
considered performed with respect to P(k) at a point in time when the
issuing of a STORE to the same address by P(k) cannot affect the
value returned by the LOAD.   A STORE by P(i) is considered performed
with respect to P(k) at a  point in time when an issued LOAD to the
same  address by P(k) returns  the value defined by  this STORE (or a
subsequent STORE to the same  location).  An access is performed when
it is performed with respect to all processors.

Definition  2 describes  the  notion  of globally  performed  for
LOADs.

      Definition 2: Performing a LOAD Globally A LOAD is globally
preformed if it  is performed and if the STORE that is the source of
the returned value has been performed.

      Acquire and release accesses are synchronization accesses.  An
acquire synchronization access is performed to gain access to a set
of shared locations.  A release synchronization access grants this
permission.  An acquire is accomplished by reading a shared location
until an appropriate value is read.

      The release consistency model is usually implemented, as a
release access is issued after all previous LOAD and STORE accesses
are performed.  However, in the definition of the release
consistency, a release access is allowed to be performed, after all
previous LOAD and STORE accesses are performed.  In other words, a
release access is allowed to be issued, before all previous LOAD and
STORE accesses are performed.  In this case, the processor, acquires
the value written by the release, should  confirm all previous LOAD
and  STORE accesses are performed.  However, the processor, which
issued the release, does not have to wait all previous LOAD and
STORE accesses are performed.  Two efficient  release consistency
systems  using  the above  method  are described.

      The first  system uses the method where the  acquiring
processor and the memory system can get information about all
previous accesses the releasing processor done before the release
access.   With this information, the acquiring processor can confirm
all previous LOAD and STORE accesses have been performed.  This
system consists of processor modules, memory modules, and connection
media among them (Fig. 1).  The processor module issues the release
access after all previous accesses are issued  without waiting the
accesses are  performed.  It  has the memory access input buffer.
The  memory subsystem has also the memory access  input buffer.   The
connection media ...