Browse Prior Art Database

An Automated Clock Generator for Card-Level Boundary Scan

IP.com Disclosure Number: IPCOM000112480D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 141K

Publishing Venue

IBM

Related People

Atallah, FI: AUTHOR [+2]

Abstract

The use of Boundary Scan (BS) at the card level has grown in popularity recently as chip manufacturers face tougher challenges in accessing Integrated Circuit (IC) pins for testing. This method utilizes electronic rather than physical testing to provide an off-chip communication path for internal self-testing and a method for measuring chip-to-chip interconnection. Penalties for implementation include an increased number of pins and increased cost [1].

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

An Automated Clock Generator for Card-Level Boundary Scan

      The use of Boundary Scan (BS) at the card level has grown in
popularity recently as chip manufacturers face tougher challenges in
accessing Integrated Circuit (IC) pins for testing.  This method
utilizes electronic rather than physical testing to provide an
off-chip communication path for internal self-testing and a method
for measuring chip-to-chip interconnection.  Penalties for
implementation include an increased number of pins and increased cost
[1].

      The 5-wire BS interface bus proposed by the Joint Test Action
Group (JTAG) includes a test clock (TCK) pin which is used to
synchronize control and transfer operations on the test bus.  This
control is achieved with a clock chopper which generates two Level
Sensitive Scan Design (LSSD) clocks.  The first clock (C), which is
generated on the rise of (TCK), captures data at the input of a Test
Access Port (TAP), while the second clock (B), which is generated at
the fall of (TCK), changes the TAP output.  This disclosure provides
a method for generating these LSSD clocks from the reference signal
(TCK) over a broad range of frequencies.

      A simplified block diagram and timing diagram of the circuit is
presented in Fig. 1.  To generate self-adjusted pulsewidths for the B
and C clock signals using purely digital design techniques, the
propagation delay of a ring oscillator is adjusted in discrete steps
to control the timing of a clock chopper.  The propagation delay in
the clock chopper is determined by the number of delay blocks in the
circuit, and the pulse widths are initiated by the rise and fall of
the reference input.  The output of the oscillator is compared with
TCK using a standard phase detector [2], which controls taps or
latched outputs to adjust propagation delay in both the oscillator
and clock chopper.  A self-adjusting pulse width is advantageous
because it satisfies aggressive test speeds while insuring
non-overlap of pulses for safe latch operation, and conversely takes
advantage of slower speeds by allowing more time for latches to
capture or load data.

      A detailed schematic of the disclosure is illustrated in Fig.
2, and a detailed schematic of the  first stage of the ring
oscillator and clock chopper is illustrated in Fig. 3.  For
simplicity, only the C clock generation is shown.  When the circuit
is powered up, the free running oscillator generates a timing signal
(IN) for comparison to TCK.  Initially, the oscillator runs at its
slowest frequency.  The phase detector generates two signals (UP) and
(DOWN) based on whether the internal or reference clock is ahead.  In
this case, if TCK is ahead of the ring oscillator, a "high" signal is
generated at the detector output (UP), and sent to the first latch
which controls the first tap of the oscillator.  The data and C clock
of the first latch are wired to VDD so that a high from the phase
d...