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Protocol Extensions to Microprocessor Memory Bus to Support Extend Extended Address Space

IP.com Disclosure Number: IPCOM000112484D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+3]

Abstract

Two types of address space can be defined by an architecture. The first is called (normal) memory space and generally speaking, addresses DRAM memory locations (although it is possible to use this space for memory-mapped I/O access as well). The second address space is called the Direct Store space and is generally used for mapping of I/O devices and sub-systems. The two address spaces are distinguished during the address translation process by a bit in the segment register. In addition, accesses to the Direct Storage Space replace their upper four bits used to index into the segment register with an additional 10 bits of address and 22 bits of flags that must be sent along with the storage access.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 73% of the total text.

Protocol Extensions to Microprocessor Memory Bus to Support Extend
Extended Address Space

      Two types of address space can be defined by an architecture.
The first is called (normal) memory space and generally speaking,
addresses DRAM memory locations (although it is possible to use this
space for memory-mapped I/O access as well).  The second address
space is called the Direct Store space and is generally used for
mapping of I/O devices and sub-systems.  The two address spaces are
distinguished during the address translation process by a bit in the
segment register.  In addition, accesses to the Direct Storage Space
replace their upper four bits used to index into the segment register
with an additional 10 bits of address and 22 bits of flags that must
be sent along with the storage access.

      The protocol for normal memory accesses uses only a 32-bit
address, and does not offer room to present the additional address or
flags associated with the Direct Store access.  One solution to this
problem is simply to expand the number of address bits going out of
the chip, but the economics of chip cost versus the overall gain in
utility makes this a net loss.  In addition, there may exist devices
on the bus that only look at the 32-bit address space, and they need
to know NOT to respond during Direct Store accesses to addresses that
happen to use these 32 bits as part of a larger address.

      To solve this problem, we expanded the bus protocol to allow
...