Browse Prior Art Database

Testing a Processor Chip in All System Environments

IP.com Disclosure Number: IPCOM000112490D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Bryant, CD: AUTHOR [+4]

Abstract

Disclosed is a way for a given processor to be tested in any system environment. The verification engineer can create a limitless set of timing scenarios on the processor's external pins. These scenarios can be generated either randomly or specifically during simulation of the processor chip. Some of the timing scenarios include system memory read and write latency, external interrupt frequency, and alternate bus master operation types and frequency. The manner in which this is done is described next.

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This is the abbreviated version, containing approximately 60% of the total text.

Testing a Processor Chip in All System Environments

      Disclosed is a way for a given processor to be tested in any
system environment.  The verification engineer can create a limitless
set of timing scenarios on the processor's external pins.  These
scenarios can be generated either randomly or specifically during
simulation of the processor chip.  Some of the timing scenarios
include system memory read and write latency, external interrupt
frequency, and alternate bus master operation types and frequency.
The manner in which this is done is described next.

      Several behaviorals are created and built into the simulation
model, which includes the processor chip under test.  These
behaviorals take the place of other supporting chips in the system,
such as system memory, I/O devices, bus arbiter, etc.  They are coded
in such a way as to allow any timing patterns to be generated on the
processor's I/O pins but still follow correct protocol.  This is
accomplished within each behavioral by coding internal counters
associated with each I/O pin which count the number of cycles the
signal is activated/deactivated.  When these counters reach a
pre-defined value, the associated pin is then deactivated/activated.

      These predefined values or parameters are set up by the
verification engineer and are generated either specifically or
randomly by the simulation control program.  This program parses out
the parameters, preloading them into arrays contained...