Browse Prior Art Database

Designing for Architected Registers in a Minimal Area Allocation

IP.com Disclosure Number: IPCOM000112504D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

East, RE: AUTHOR [+2]

Abstract

Typically designs, in this case a microprocessor design, of successive generations must conform to prior architectural restrictions and functional specifications yet potentially with different constraints, such as silicon chip die area, to implement such features. Disclosed is a technique that minimizes the silicon chip die area required for implementation of architected registers or similar elements of the design.

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Designing for Architected Registers in a Minimal Area Allocation

      Typically designs, in this case a microprocessor design, of
successive generations must conform to prior architectural
restrictions and functional specifications yet potentially with
different constraints, such as silicon chip die area, to implement
such features.  Disclosed is a technique that minimizes the silicon
chip die area required for implementation of architected registers or
similar elements of the design.

      Taking advantage of an on-board co-processor (a microcode
sequencer) that handled other microprocessor operations, the
architected registers were relegated to a Static Random Access Memory
array (versus discrete registers) that the co-processor retrieved or
stored (and manipulated) when required.  The silicon chip die area
savings was significant.  A state machine could serve the purpose of
the co-processor if the overall area savings justified it.  The
drawback of this approach is the register access time is slower, but
in many design points such as this one where silicon chip die area is
more critical than a minor performance degradation, it's an
appropriate design trade off.