Browse Prior Art Database

Low Power/High Speed DRAM

IP.com Disclosure Number: IPCOM000112523D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Hardell Jr, WR: AUTHOR

Abstract

This method is used to maintain low power while reducing the first access latency to a DRAM. The input latency is reduced by having the ability to enable the input receivers before RAS is activated. This can, also, reduce the window (setup + hold time) that the row needs to be active. The power is kept low in stand-by mode by disabling the receivers with a Chip Select (CS). At the system level, the row address and CS active would be sent to the DRAMs at the same time. During the Row setup-time the memory controller is decoding the upper address bits to determine which set of DRAMs (bank) should have RAS dropped.

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Low Power/High Speed DRAM

      This method is used to maintain low power while reducing the
first access latency to a DRAM.  The input latency is reduced by
having the ability to enable the input receivers before RAS is
activated.  This can, also, reduce the window (setup + hold time)
that the row needs to be active.  The power is kept low in stand-by
mode by disabling the receivers with a Chip Select (CS).  At the
system level, the row address and CS active would be sent to the
DRAMs at the same time.  During the Row setup-time the memory
controller is decoding the upper address bits to determine which set
of DRAMs (bank) should have RAS dropped.

      The other method of increasing performance is by adding a small
buffer (probably SRAM, but possibly DRAM or another storage device)
that can hold several transfers of data (e.g. 2-8) so that a hidden
RAS pre-charged can occur or an additional Column access can be
completed in the back ground while the data in the buffer is clocked
out.  This method is used to maintain low power while reducing the
first