Browse Prior Art Database

VLSI System Level Timing Analysis

IP.com Disclosure Number: IPCOM000112524D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 159K

Publishing Venue

IBM

Related People

Elder, WH: AUTHOR

Abstract

SLETE stands for System Level ETE, which stands for Early Timing Estimator, a chip timing tool used by many CMOS products. EDS manual 3325 "Early Timing Estimator (ETE) User's Guide and Reference" provides a description of ETE.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 42% of the total text.

VLSI System Level Timing Analysis

      SLETE stands for System Level ETE, which stands for Early
Timing Estimator, a chip timing tool used by many CMOS products.  EDS
manual 3325 "Early Timing Estimator (ETE) User's Guide and Reference"
provides a description of ETE.

      The primary objective of SLETE is to support system level
timing analysis of synchronous designs using a combination of ASICs
and VTL components.  The initial version of SLETE will be developed
for the mainframe.  SLETE will be written to minimize effort required
to port it to a workstation.

      The flow chart in Fig. 1 shows the flow of SLETE operation.
The following provides an overview of SLETE operation.

SLETE uses the following types of input data:

o   Bill of Materials (BOM) that identifies the models being used for
    each chip and their hierarchical block identification

o   A wire delays file that contains the logical connectivity of the
    blocks in the design

o   SLETE models of IBM designed ASIC chips

o   ETE rules for vendor chips and non-ASIC chips such as RAMs, ROMs,
    etc.

o   Design file inputs for controlling the SLETE analysis

      The BOM and wire delay files are generated from the SLAM/ANDAP
output file.  SLAM takes in the system level BDL/S and physical
design information and sets up jobs to be run by ANDAP to analyze
networks.  The resulting wire delay file gives the interconnect delay
from chip prototype block pin to chip prototype block pin and defines
the primary inputs and outputs of the system logic.  These prototype
pins will correspond to prototype block pin ids used when the chip
SLETE model is created.

      A SLETE model will be generated by a new option on the ETE
UTILITY menu, SLETEMDL.  This model will contain only the boundary
logic and clock distribution logic, ie, the chip BDL/S will be
reduced to the logic between PIs and latches, latches and POs, logic
that goes from a PI to a PO without being latched, and any clock
generation or distribution logic.  The SLETE model language will be
pseudo BDL/S where blocks and netnames have a generic Part Usage Code
(PUC) added.  For example, AA100AA = > AA100AA@@xx, where "xx" is the
PUC which will be replaced by the user specified value in BOM2 for a
particular ASIC usage.  The use of the PUC allows SLETE to run flat
with multiple usages of the same chip.  The internal models used by
SLETE will be created on the fly for each model usage when the BOM is
processed.  There will be a unique PUC for each usage of a chip.
SLETE models will also contain all pertinent chip level timing
information for the reduced BDL/S, including RCs, don't cares, data
adjusts, phase definitions, etc.

      System level connection and delay information will come from
the SLAM/ANDAP post-processor file.  The connection information from
SLAM will be based on chip prototype blocks.  Prototype pins must be
consistent with those in the SLETE model and ETE r...