Procedure and Design to Facilitate Self Timed Implementations of Combinational Logic
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Klim, PJ: AUTHOR [+2]
AbstractTo self-time a logic partition it is normally necessary to carefully evaluate the logic time of flight to identify data dependent slow paths that can lead to logic hazards or faults. Insertion of designed delay elements solves the general problem without introducing excessive additional complexity.
Procedure and Design to Facilitate Self Timed
a logic partition it is normally necessary to
carefully evaluate the logic time of flight to identify data
dependent slow paths that can lead to logic hazards or faults.
Insertion of designed delay elements solves the general problem
without introducing excessive additional complexity.
Fig. 1 shows
a typical latch bounded combinational logic
partition called a logic group, which consists of an input register
that holds the data and a set of logic circuits that decode or
otherwise modify the data, in this case differential cascode voltage
switch, DCVS. Implied is that there is another register on the
output side, which forms the input register for another logic group.
One will notice that the logic blocks have been arranged in columns,
or 'stages', where Stage 1 are all the blocks that are driven by the
register, Stage 2 are the blocks that are driven either by the
register or Stage 1 blocks, etc. One can readily see that the data
at either the stage boundaries or the output have differing
propogation times, due to differing numbers of logic stages and
variations in wire loadings from the input register to the output.
desires to form a self-timed version of the same logic
one needs to be able to bound subsets of the logic into groupings
where the propogation time from the register to the output side of
any of the stages is the same on all the data crossing that stage
line. Again, from Fig. 1 it is apparent that it would be difficult
to self-time this representative logic since one can readily see that
some stage 2 blocks are driven by the register, disallowing a timing
partition to be made from Stage 1, for instance, since the arrival
time of the stage 1 outputs will be considerably different than the
outputs of the register fed directly to the Stage 2 blocks. If this
logic additionally is pipelined, as might be the case, then the data
in the register might have changed from that which was driven into
Stage 1 by the time the Stage 1 outputs are clocked out.
to the problem is to insert dummy circuit blocks
inline with the data that crosses stage lines, as shown in Fig. 2,
where these dummy latches are indicated with the dashed blocks. One
can see that there are an equal number of blocks to propogate through
from the register data source to the output. One can see that if the