Browse Prior Art Database

Processor Cache Sector Invalidate Signal on a Processor Bus

IP.com Disclosure Number: IPCOM000112548D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Garcia, MJ: AUTHOR [+4]

Abstract

Disclosed is a method of providing information from a processor incorporating an L1 cache to indicate to an external L2 cache that the processor is invalidating a sector of the L1 cache.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 61% of the total text.

Processor Cache Sector Invalidate Signal on a Processor Bus

      Disclosed is a method of providing information from a processor
incorporating an L1 cache to indicate to an external L2 cache that
the processor is invalidating a sector of the L1 cache.

      A processor incorporating a store-in or write back level 1 (L1)
cache can maintain coherency between the cache and main memory using
a basic MESI (Modified/Exclusive/Shared/Invalid) protocol.  In
systems incorporating a level 2 (L2) cache, the coherency between the
three storage elements (L1, L2, and main memory) must still be
maintained.

      To facilitate this, the L2 cache must maintain a copy of the L1
cache directory.  To maintain the cache directory efficiently, the L2
directory must know when a given cache sector in the L1 cache is
being invalidated.  A sector may be invalidated by any of the
following:  1) a data cache sector invalidate or a data cache sector
flush instruction is executed by the processor, 2) unmodified data in
the cache is replaced with data from another address, 3) modified
data is being cast out (written back to memory) to make room in the
cache for other data, or 4) modified data in the cache is pushed out
in response to a snoop hit in the cache.

      The data cache sector invalidate and flush operations
incorporate unique bus transaction type encoding, which can be
monitored by the L2 directory logic, while cache sector replacement
appears on the bus as a cached rea...