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Browse Prior Art Database

Discrete to Sync Clock Generator

IP.com Disclosure Number: IPCOM000112565D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Blakney, SD: AUTHOR [+2]

Abstract

This article describes a circuit that enables the MD407 Memory Tester to provide a free running clock of programmable duty cycle and frequency, synchronized to the single event clocks provided by the tester.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Discrete to Sync Clock Generator

      This article describes a circuit that enables the MD407 Memory
Tester to provide a free running clock of programmable duty cycle and
frequency, synchronized to the single event clocks provided by the
tester.

      The schematic in the Figure shows the circuit diagram for the
clock circuit.  For many test applications on the MD407, the tester
has to provide a free running clock.  If an external oscillator is
used, there is the problem of synchronizing this free running clock
to the tester clock.

      The MD407 provides up to 36 clocks which can be programmed to
occur only ONCE in a tester cycle.  In order to generate a free
running clock, many tester clocks need to be "OR'd" together to
create a clock "train" of fixed duration.

      The circuit shown in the Figure will only require 2 tester
clocks; one to start or restart the generator and one to stop it.
The clock circuit will generate a free funning clock for any duration
of the tester cycle.  The Start-stop-Restart feature will keep the
free running clock synchronized to the tester clocks; and because of
this, to the data and address outputs generated by the tester.

      The 2 programmable delays are used to set the cycle duration or
period (frequency) and the duty cycle of the free running clock.