Browse Prior Art Database

Improved Boundary Scan Design for VLSI Circuit Testing

IP.com Disclosure Number: IPCOM000112568D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 8 page(s) / 210K

Publishing Venue

IBM

Related People

Radke, CE: AUTHOR [+2]

Abstract

Described is a hardware implementation for an improved boundary scan structure that allows testing of Very Large-Scale Integrated (VLSI) circuits using a low cost tester while maintaining a high product quality level.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 35% of the total text.

Improved Boundary Scan Design for VLSI Circuit Testing

      Described is a hardware implementation for an improved boundary
scan structure that allows testing of Very Large-Scale Integrated
(VLSI) circuits using a low cost tester while maintaining a high
product quality level.

      The implementation involves an improved boundary scan latch
arrangement for delay testing, so that a low cost tester can be used
to obtain the same high delay test effectiveness as obtained from
high cost testers, such as a per-pin tester.

      Level Sensitive Scan Design (LSSD) circuits have been widely
used in computer circuitry.  Fig. 1 shows a block diagram of a
typical LSSD circuit structure.  Input Boundary Logic (IBL) receives
signals from Primary Inputs (PIs) and feeds the signals to scannable
Shift Register Latches (SRLs).  The outputs of the SRLs feed the
Internal Logic (IL), and the outputs of the IL either go directly to
chip outputs or feed second SRLs.

      The number of SRLs and their arrangements are determined by
circuit designers.  The SRLs that do not feed another SRL through
internal logic will feed the Output Boundary Logic (OBL) and go to
the chip Primary Outputs (POs).  In order to reduce the cost of VLSI
circuits, the utilization of Boundary Scan Latches (BSLs) is well
known.  The advantages of using BSLs are two-fold, such as: a) to
reduce the required tester pin-count and b) to improve testing of the
interconnections between chips.  It is also used in the
implementation of Built-In Self-Test (BIST) circuitry.

      Fig. 2 shows a block diagram of an LSSD circuit with input and
output BSLs implemented in the LSSD design.  Fig. 3 shows a one-bit
circuit arrangement of a BSL.  Latch L1 is used to control clocks A
and C.  Clock A is a scan clock which is used to control the scan-in
data.  Clock C is a system clock used to control the system data
input.  Latch L2 is controlled by a single B clock, and it shifts the
ocntent of latch L1 into latch L2 while active.  Latches L1 and L2
contain the basic units of the BSLs.  At the system mode, a
multiplexer (MUX) selects the incoming signal from a Primary Input
(PI).  At the test mode, the MUX selects the signal coming from latch
L2.  Units of latches L1 and L2 are connected as scan chains that are
used to scan in the test data and to scan out a response during
testing.  ;p.  However, there are disadvantages in using the BSLs.  A
major drawback is the degradation of the delay test.  As the speed of
digital circuits increases and the demand for higher chip densities
increases, the delay test has become a critical phase of the VLSI
tests.  The conventional BSL arrangement is not sufficient to detect
small-size delay slacks and therefore can degrade the quality of the
product.

      Fig. 4 shows a block diagram of untested delay slacks caused by
boundary scan designs.  A four-bit BSL is used to illustrate the
disadvantages of using BSLs.  From res...