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Efficient Use of Branch History Table in Architectures that Use Counter and Condition Register-Based Branch Instructions

IP.com Disclosure Number: IPCOM000112577D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Levitan, DS: AUTHOR [+2]

Abstract

Described is an efficient way to use a Branch History Table (BHT) in architectures that use counter and condition-based branch instructions. Since the branch outcome of a counter and condition-based branch can be predicted quite accurately by the counter value alone, the history of such a branch is not kept in the BHT to better utilize the BHT.

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Efficient Use of Branch History Table in Architectures that Use Counter
and Condition Register-Based Branch Instructions

      Described is an efficient way to use a Branch History Table
(BHT) in architectures that use counter and condition-based branch
instructions.  Since the branch outcome of a counter and
condition-based branch can be predicted quite accurately by the
counter value alone, the history of such a branch is not kept in the
BHT to better utilize the BHT.

      There are two types of branch instructions in the preferred
architecture: unconditional and conditional.  An unconditional branch
instruction specifies that the next instruction to be executed be the
instruction at the address specified by the branch instruction.  A
conditional branch instruction specifies that the next instruction to
be executed is determined by the outcome of the specified branch
condition.

      The conditional branch instructions in the preferred
architecture use two types of conditions:  count register-based and
condition register-based.  The count register-based conditions are
typically of "equal to zero" or "not equal to zero", and are used in
the counter-based loop of instructions.  Because of the way they are
used in loops of instructions, the outcome of count register-based
conditions are easy to predict.  The condition register based
conditions are more difficult to predict, since the conditions are
typically the outcomes of comparing two operands.  The branch
condition in the conditional branch instructions in the prefe...