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Dynamic Hardware Translation of a 2N-Bit Field to an M-Bit Field

IP.com Disclosure Number: IPCOM000112586D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Carle, G: AUTHOR [+3]

Abstract

This article explains a hardware mechanism used to dynamically translate an N-bit field to an M-bit field index under a variable N-bit Mask (N>M).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 59% of the total text.

Dynamic Hardware Translation of a 2N-Bit Field to an M-Bit Field

        ----------------------------------------------
        |          0                          31     |
        |      out-------------------------------    |
        |----<----|         UMR                 <-----
        |         -------------------------------in
Clock   |                        |
--------+------------------------|
      | |          0             |            31
     ---+-     out-------------------------------
     |AND|     ---|         SOURCE REG          |
     -----     |  -------------------------------
       |       ---------------------------------------
       ---------------------------                   |
                   0             |            31     |
                  ---------------V---------------    |
                  |         IUR                 <-----
                  -------------------------------in

Fig. 1

      This article explains a hardware mechanism used to dynamically
translate an N-bit field to an M-bit field index under a variable
N-bit Mask (N>M).

      Applications i...