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Atmospheric Pressure In-Situ Doped Polysilicon Deposition Method for Filling High Aspect Ratio Trenches

IP.com Disclosure Number: IPCOM000112593D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 165K

Publishing Venue

IBM

Related People

Gruetzmacher, DA: AUTHOR [+4]

Abstract

Atmospheric pressure in-situ doped polysilicon deposition is proposed for the void-free filling of high aspect ratio trench storage capacitors for 256 Mb DRAM and beyond. For higher density DRAMs, the trench-opening dimensions are scaled down along with cell area and minimum lithography feature size. With decreasing trench-opening dimensions, trenches are etched deeper and deeper to minimize the loss of surface area available for capacitance, thereby increasing the aspect ratio of the trench. For the 256 Mb DRAM, the aspect ratio of the trench storage capacitor is expected to range from 16 to 40. When conventional polysilicon deposition techniques are used to fill high aspect ratio trenches, voids are formed inside due to the nearly vertical sidewall profile angle.

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Atmospheric Pressure In-Situ Doped Polysilicon Deposition Method
for Filling High Aspect Ratio Trenches

      Atmospheric pressure in-situ doped polysilicon deposition is
proposed for the void-free filling of high aspect ratio trench
storage capacitors for 256 Mb DRAM and beyond.  For higher density
DRAMs, the trench-opening dimensions are scaled down along with cell
area and minimum lithography feature size.  With decreasing
trench-opening dimensions, trenches are etched deeper and deeper to
minimize the loss of surface area available for capacitance, thereby
increasing the aspect ratio of the trench.  For the 256 Mb DRAM, the
aspect ratio of the trench storage capacitor is expected to range
from 16 to 40.  When conventional polysilicon deposition techniques
are used to fill high aspect ratio trenches, voids are formed inside
due to the nearly vertical sidewall profile angle.  The Figure is a
TEM cross section illustrating the void formation in a 0.25 &mu.m
square trench 8.5 &mu.m deep.  Amorphous silicon deposition
conditions could avoid the void formation.  However, amorphous
silicon deposition has the following drawbacks: (1) deposition rate
is low, about 3 nm/min., and (2) doping concentration of dopants
achievable in amorphous silicon is less than that of conventional
polysilicon.  Lower deposition rate gets translated into higher
processing costs.  Very high dopant concentration (1 X 100  /cm3  or
higher) is desirable to minimize any depletion effects...