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Browse Prior Art Database

Self-Precharged Single Clock DRAM

IP.com Disclosure Number: IPCOM000112600D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 91K

Publishing Venue

IBM

Related People

Miyatake, H: AUTHOR

Abstract

In conventional DRAMs, whether double-clocked (clocked by /RAS and /CAS) or single-clocked (clocked by /CE), their control circuits start the access phase operation at the leading edge of the main clock (/RAS or /CE) and begin the precharge phase operation at the trailing edge of the main clock (/RAS or /CE). (See Fig. 1 for the timing chart.) In other words, /RAS or /CE must remain active until the DRAM internal state becomes ready for the precharge phase operation, and its trailing edge gates the cycle time which, in turn, determines the data transmission rate. Of course, users must control two timings of the main clock (/RAS or /CE): the leading edge and the trailing edge.

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This is the abbreviated version, containing approximately 52% of the total text.

Self-Precharged Single Clock DRAM

      In conventional DRAMs, whether double-clocked (clocked by /RAS
and /CAS) or single-clocked (clocked by /CE), their control circuits
start the access phase operation at the leading edge of the main
clock (/RAS or /CE) and begin the precharge phase operation at the
trailing edge of the main clock (/RAS or /CE).  (See Fig. 1 for the
timing chart.) In other words, /RAS or /CE must remain active until
the DRAM internal state becomes ready for the precharge phase
operation, and its trailing edge gates the cycle time which, in turn,
determines the data transmission rate.  Of course, users must control
two timings of the main clock (/RAS or /CE): the leading edge and the
trailing edge.

      The newly proposed DRAM control method relieves users from the
timing constraint at the trailing edge of the main clock (/RAS or
/CE) and makes it easy to use it at the minimum cycle time with the
highest data transmission rate.

      In this new control method, one of the internal clock signals
at the end of the access phase is used to reset the internal main
clock, CLK, and resetting the CLK triggers the precharge phase
operation of the internal control circuits.  CLK is set by the
leading edge of the external main clock (/RAS or /CE), and this
transition initiates the access phase operation of the internal
control circuits.  Thus, users only have to control the leading edge
of the external main clock.

      There are some degrees of freedom in selecting the signal which
resets the internal main clock signal, CLK.  Generally speaking, DRAM
can start its precharge phase operation after data are exchanged
between the bit lines and d...