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Address Pipelining with a Flexible Control Mechanism for Shared Bus Protocols

IP.com Disclosure Number: IPCOM000112623D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 95K

Publishing Venue

IBM

Related People

Allen, MS: AUTHOR [+4]

Abstract

This article descibes the protocol that is implemented on a microprocessor to allow address pipelining to occur, yet still maintain the required flow control capability. In this context, flow control means the ability to extend the address time for slower devices that cannot process the address in the minimum address tenure time, and the ability to force the bus master to withdraw the current transaction and run it again at a later time (this is called a "retry" of the bus transaction). This is the mechanism utilized by hardware to enforce the coherency protocol as well as to allow devices with finite queue depths to attach to the bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Address Pipelining with a Flexible Control Mechanism for Shared Bus
Protocols

      This article descibes the protocol that is implemented on a
microprocessor to allow address pipelining to occur, yet still
maintain the required flow control capability.  In this context, flow
control means the ability to extend the address time for slower
devices that cannot process the address in the minimum address tenure
time, and the ability to force the bus master to withdraw the current
transaction and run it again at a later time (this is called a
"retry" of the bus transaction).  This is the mechanism utilized by
hardware to enforce the coherency protocol as well as to allow
devices with finite queue depths to attach to the bus.

      Address pipelining is a technique that allows the address phase
of subsequent bus operation(s) to overlap with the data phase of the
current operation.  This can improve bus throughput because most of
the bus traffic involves burst transfers in which a lot of data is
transferred with one address; for example, the preferred
microprocessor transfers eight 32-bit words for each 32-bit address
in a burst transfer.  Overlapping subsequent address phases with the
lengthy data phase achieves a pipeline effect which can minimize the
idle time on the data bus.  In multiprocessor systems in particular,
there can be a large amount of inter-processor communication, much of
which can be address-only bus operations that do not require the data
bus.  By address pipelining, these operations can have a negligible
impact on data bus bandwidth.

      The flow control mechanism employed is a handshake protocol
between the bus master and the rest of the system.  Once a bus master
has won arbitration for the address bus and presents the address to
the bus, it must continue to drive the valid address until it
receives acknowledgement from the system.  In the preferred
microprocessor bus protocol, this acknowledgement is the AACK
(Address ACKnowledge) input to the bus master.  Delaying the
assertion of AACK provides more time for slower devices to sample and
process the address.  An example could be large caches which must
snoop the address but have several chip crossings to determine if a
cache hit has occurred.

      It is desirable to pipeline addresses on the microprocessor
interface, particularly in a multiprocessor system where the bus
utilization is high; however, the bus interface must provide flow
control capability, which can...