Browse Prior Art Database

Indirect Isochronous Data Transfer on a Parallel Bus

IP.com Disclosure Number: IPCOM000112634D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 231K

Publishing Venue

IBM

Related People

Cresp, J: AUTHOR [+3]

Abstract

Disclosed is a mechanism which allows any device which may need a method of isochronous communication over a Parallel Bus Architecture machine, to do so via two or more adapters. It applies to communication adapters which normally pass data between them over a parallel bus but the transfer needs sometimes to be isochronous. A specific use is transferring real-time speech data rather than data protocol methods.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 26% of the total text.

Indirect Isochronous Data Transfer on a Parallel Bus

      Disclosed is a mechanism which allows any device which may need
a method of isochronous communication over a Parallel Bus
Architecture machine, to do so via two or more adapters.  It applies
to communication adapters which normally pass data between them over
a parallel bus but the transfer needs sometimes to be isochronous.  A
specific use is transferring real-time speech data rather than data
protocol methods.

      A knowledge of Time Division Multiplex (TDM) system, Software
Queuing/Semaphore and isochronous behaviour is assumed for this
description.  The problem solved in this disclosure is summarized
below.

o   Adapters which are Indirectly attached to the source of
    Isochronous data need a mechanism to communicate with the
    Directly attached adapters.

o   Indirectly attached adapters which are isochronous are normally
    TDM based and work from a master clock from one of the Link
    Interfaces.

o   Indirectly attached adapters which are isochronous which do not
    use TDM interfaces have no master clock to stay isochronous with
    and data loss may occur.

      (An Indirectly attached adapter may be a card which processes
incoming/ outgoing channel data for any channel on the link for
example (E1/T1/J1) and has no link to the E1/T1 adapter except
through a Parallel I/O bus like ISA, Microchannel, EISA, VME etc.).

      A new ISA, Microchannel or VME bus signal cannot be placed on
the bus to allow a master clock system for synchronisation.  Data
cannot be routed every 125 microseconds over a Parallel Bus
architecture since the normal mechanisms of an adapter sending data
is to Interrupt the processor or to raise a request to send the data
via Direct Memory Access (DMA).  These mechanisms can only be used
efficiently with larger packets of data to be sent for example, every
'n' milliseconds.  For a System with more than one line interface,
the time when the 'n' millisecond starts will be random.  The 'n'
milliseconds is normally derived from the link clock to which they
are attached ie n = k x Derived 125 microsecond frame pulses from the
network, and, k = constant ie.  8 for n=1 millisecond.  The maximum
packet size of the data is 'k' bytes to be transferred per channel.
A solution could have been to have a 125 microsecond timer on the
Indirectly attached adapter to also generate and Interrupt every 'n'
milliseconds so that data can be copied between them.

      Copying data indirectly via system memory between the adapters
is possible, can be isochronous, but relies on one assumption.  The
Interrupt rate of the line interface adapter and the FAX adapter must
be identical or else there will be a corresponding drift in the time
between the interrupts otherwise the following data loss will occur.

o   Data is lost in the Line Interface to FAX adapter direction if
    the Line Interface interrupts faster than...