Browse Prior Art Database

N-Way Superscalar N-Deep Pipeline Processing Control Register

IP.com Disclosure Number: IPCOM000112638D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Borkenhagen, JM: AUTHOR [+2]

Abstract

An instruction Processing Control Register that supports multiple instruction processing modes in N-way superscalar N-deep pipelined processors is disclosed. The Processing Control Register (PCR) helps identify and patch bugs in control logic that handles bypasses, stalls, re-execution, and branches. This area of control logic has a history of higher than average bug rates due to dependencies between concurrently executing instructions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

N-Way Superscalar N-Deep Pipeline Processing Control Register

      An instruction Processing Control Register that supports
multiple instruction processing modes in N-way superscalar N-deep
pipelined processors is disclosed.  The Processing Control Register
(PCR) helps identify and patch bugs in control logic that handles
bypasses, stalls, re-execution, and branches.  This area of control
logic has a history of higher than average bug rates due to
dependencies between concurrently executing instructions.

      An instruction Processing Control Register (PCR) was
implemented on a 4-way superscalar 3-deep pipelined processor with a
six-bit register.  The six register bits control the degree of
pipelining and superscaling on the processor as follows:

No Dispatch (bit 0) When this bit is a binary "0", instructions are
           allowed to be issued from stage 0 of the pipe.  When this
           bit is a binary "1", no instructions are issued from stage
           0 of the pipe.

No Multiple Dispatch (bit 1) When this bit is a binary "0", up to
           four instructions are issued from stage 0 each processor
           cycle.  When this bit is a binary "1", only one
instruction
           is dispatched from stage 0 each processor cycle.

No Dispatch if Stage 1 Stall (bit 2) When this bit is a binary "1",
           no instructions will be dispatched from stage 0 if any
           instructions are stalled in stage 1.

No Dispatch if Stage 1 Valid (bit 3) When this bit is a binary "1",
           no instructions will be dispatched if there are any valid
           instructions in stage 1.

No Dispatch if Stage 2 Valid (bit 4) When this bit is a binary "1",
           no instructions will be dispatched if there are any valid
           instructions in stage 2.

Instruction Step (bit 5) When this bit is a binary "1", bit 0 (No
           Dispatch) will be set when any valid instruction in stage
2
           completes execution.

      Bits in the PCR can be loaded with processor clocks either
stopped or running through the scan communications interface.

The following are several examples of how the PCR can be used to
detect and fix bugs:

Isolate a failing instruction (debug). Up to 12 instructions will be
           in various stages of execution during each clock cycle on
           the processor, making it difficult to isolate the source
of
           a logic design failure.  By setting the PCR to "011111"
           (single step mode) before starting the clocks, only a
           single instruction wil...