Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Fault Model Verification Technique

IP.com Disclosure Number: IPCOM000112646D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Dibrino, M: AUTHOR [+3]

Abstract

Disclosed is a technique that verifies fault models generated by either automatic or manual methods.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 88% of the total text.

Fault Model Verification Technique

      Disclosed is a technique that verifies fault models generated
by either automatic or manual methods.

      A fault model is a test representation of circuit schematics.
It is used to generate test patterns for a manufacturing test.

      Once fault models are generated, it is necessary to verify
their functional correctness with respect to design specifications.
In general, a logic designer uses a 'behavior'-type language (e.g.,
DSL) to model the logic function and use a simulator (e.g., TEXSIM)
to simulate functionality.

The following technique is developed to verify fault models:

1.  Each circuit macro has a specific fault model.  The first step is
    to expand it to a logic model that only contains primitive gates.

2.  Using TestBench 6000 (an IBM test generator running in RS6000) or
    an equivalent test generator, one can generate test patterns that
    provide 100% test coverage and store these patterns in a file.
    The expected response of each pattern is also stored in a file.

3.  Convert these test patterns and their responses into a target
    simulator (e.g., TEXSIM) format.

4.  Simulate these newly-formatted test patterns on a DSL that
    represents the behavior of the circuit macro under test.

5.  For each test pattern, compare TB6000 response with the simulated
    result of a DSL pattern.

6.  If all responses of all test patterns are matched, we conclude
    that both t...