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Browse Prior Art Database

Method for Driving Excessively Loaded Master/Slave-Type Busses

IP.com Disclosure Number: IPCOM000112650D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 268K

Publishing Venue

IBM

Related People

Thomsen, PM: AUTHOR

Abstract

Master/slave busses, such as the Micro Channel*, typically allow a feature adapter to be plugged into slots to increase overall system functionality. But due to the speeds at which these busses are being run, there becomes a limit to the number of adapters that can be plugged into a system. High capacitive loading by the adapters leads to signal integrity problems such as transmission line effects and current drive problems by bus drivers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 34% of the total text.

Method for Driving Excessively Loaded Master/Slave-Type Busses

      Master/slave busses, such as the Micro Channel*, typically
allow a feature adapter to be plugged into slots to increase overall
system functionality.  But due to the speeds at which these busses
are being run, there becomes a limit to the number of adapters that
can be plugged into a system.  High capacitive loading by the
adapters leads to signal integrity problems such as transmission line
effects and current drive problems by bus drivers.

      In addition to feature adapters existing on these busses,
designers incorporate integrated adapters onto the system planar to
add functionality to the system without taking up a feature slot.
This further complicates signal integrity problems as the integrated
adapter also presents a load to the bus.

      This invention targets systems that merge integrated bus master
adapters onto a feature card bus.  Fig. 1 illustrates a typical
system with this configuration.

      As can be seen in Fig. 1, this type of configuration has the
feature slots and integrated devices connected to the same bus.

      In the case of the Micro Channel this type of system
configuration runs into problems with capacitive loading.  The Micro
Channel specifies a certain maximum capacitance for the entire bus,
and with the above configuration capacitive loading is sure to be
exceeded.  As a consequence, signal integrity and buffer drive
problems will exist.  In addition, future trends are to integrate
more functions into the system which will make the problem even worse
in the future.

      This invention addresses this situation by separating the
feature slots and integrated devices control signal bus into two
separate busses.  This involves doubling the buffers to create the
two control signal busses.  The address and data busses are not
split, and the buffers are not repeated in order to create a cost
effective design.  Fig. 2 shows the proposed configuration:

      This configuration allows critical edge-triggered signals of
the Micro Channel to be driven into smaller loads, thus reducing
signal integrity and current drive problems.  The Address and Data
busses are not as critical as the Control signals and therefore do
not demand as much attention.

      This invention concentrates on controlling the direction
enables of the Control bus buffers so that bus contention does not
occur on the processor side of the bus.  There are three conditions
that exist on the Micro Channel bus that must be considered:

Slave & 3rd Party DMA Transfers (Processor drives Control bus signals
to Micro Channel).
1st Party DMA Transfers (Adapter card drives Control bus signals to
Processor).
Peer-to-Peer Transfers (Adapter card drives Control bus signals to
another adapter).

      Each of these three transfer methods require different buffer
direction enables, and each will be discussed in detail.  For the
purposes of th...