Browse Prior Art Database

DEMI Cache Management Policy for a Coherent DMA Cache on a Snooping Memory Bus

IP.com Disclosure Number: IPCOM000112653D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+4]

Abstract

This disclosure presents a policy which reduces Direct Memory Access (DMA) latency and reduces complextiy of DMA cache controller design. This disclosure is an adaptation of the Modified/Exclusive/Shared/Invalid (MESI) cache management policy (as used in the PowerPC* 601 chip) to address the special needs of a DMA cache. (References: IBM PowerPC I/O Architecture and the PowerPC 601 User's Manual, Chapter 4, p. 10.)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

DEMI Cache Management Policy for a Coherent DMA Cache on a Snooping
Memory Bus

      This disclosure presents a policy which reduces Direct Memory
Access (DMA) latency and reduces complextiy of DMA cache controller
design.  This disclosure is an adaptation of the
Modified/Exclusive/Shared/Invalid (MESI) cache management policy (as
used in the PowerPC* 601 chip) to address the special needs of a DMA
cache.  (References: IBM PowerPC I/O Architecture and the PowerPC 601
User's Manual,  Chapter 4, p. 10.)

The MESI cache management policy employs 4 cache states:

                  Modified  (M)

                  Exclusive (E)

                  Shared    (S)

                  Invalid   (I)

      When the data in the cache must be modified, the cache
controller first executes the memory bus operations required to
obtain exclusive access to the requested sector, enters the Modified
state, and only then allows the data modification to proceed, i.e.,
the MESI cache management policy uses a pre-ownership ethic with
respect to modification of cached data.

      Applying such a policy to a DMA cache has the disadvantage of
adding "wait states" to I/O channel latency (after an I/O bus master
initiates a DMA transfer to system memory) while the I/O Channel
Controller (IOCC) executes the memory bus operations required to
obtain exclusive access to the requested memory sector.

      The protocol disclosed here is a DMA cache management policy
which reduces I/O channel latency by using a post-ownership ethic
with respect to modification of its DMA cache data by an I/O bus
master.  This policy, referred to here as DEMI, also employs 4 cache
states:

                  Dirty     (D)

                  Exclusive (E)

                  Modified  (M)

                  Invalid   (I)

      When an I/O bus master initiates a transfer of data to system
memory, the DMA cache enters the Dirty state and transfer of data
from the bus master to the DMA cache is allowed to proceed without
"wait states", because the IOCC uses a post-ownership ethic with
respect to modification of cache data:  n...