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Reuse of Logic Synthesis Test Patterns for Generating Tests

IP.com Disclosure Number: IPCOM000112660D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Baur, U: AUTHOR [+3]

Abstract

This article describes a method with which the generation of test patterns for scan path designs using the stuck-fault model can be integrated with a system for the synthesis of the logic being tested. In its most basic form, the method allows one to save the test patterns created during the synthesis of the logic and to use these in order to create test patterns for use during the manufacturing process.

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Reuse of Logic Synthesis Test Patterns for Generating Tests

      This article describes a method with which the generation of
test patterns for scan path designs using the stuck-fault model can
be integrated with a system for the synthesis of the logic being
tested.  In its most basic form, the method allows one to save the
test patterns created during the synthesis of the logic and to use
these in order to create test patterns for use during the
manufacturing process.

The implementation of the idea requires:

o   A system for logic synthesis which includes a test generator for
    removing redundant logic.

o   An interface to a program for test manufacturing pattern
    generation.

      When synthesizing logic, a test pattern is created which allows
the testing of input and output pins for the logic blocks.  According
to the idea, these patterns are stored during the synthesis process.
After completion of the synthesis process, the stored patterns are
passed to the test pattern generation program together with the
designed logic.  A simple translation program is used to translate
the stored test patterns into the Basic Design Language of Control
(BDL/C) format.  The BDL/C format test pattern can then be used for
deterministic test generation in the test system.