Browse Prior Art Database

Shared Texture Map Memory in a Multi-Rasterizer System

IP.com Disclosure Number: IPCOM000112664D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 8 page(s) / 256K

Publishing Venue

IBM

Related People

Bowen, AD: AUTHOR [+2]

Abstract

A series of embodiments for providing a shared memory mechanism for texture map memory in a parallel rasterizer system is disclosed. Each embodiment has benefits in terms of flexibility and cost.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 26% of the total text.

Shared Texture Map Memory in a Multi-Rasterizer System

      A series of embodiments for providing a shared memory mechanism
for texture map memory in a parallel rasterizer system is disclosed.
Each embodiment has benefits in terms of flexibility and cost.

      Background - Texture mapping is the application of a two- or
three-dimensional image to a surface based on a (typically) linear
transform.  The most common method of applying a texture to a surface
is to use a secondary set of interpolators to interpolate the texture
map address across the surface in step with the surface's (x,y,z)
coordinate.

      In a high-performance graphics system, the interpolation
process is performed by parallel rasterizer engines.  The number of
engines may be any number, with ranges from 4 to 64 engines being
common.  A texture map may be of any size and depth, although
1'K'*1'K'*32%'bits' is common.  This equates to 4MBytes of storage,
with a cost of approximately $64 and a power dissipation of
approximately 8 watts.  For an 8-way parallel system, the texture
memory alone adds $512 to the base cost (8*'$'64), and consumes 64
watts of power.  This amount of power consumption is not acceptable
for adapters that must reside within a desk-top workstation.
Additionally, the space required for the 64 4-Mbit DRAM devices is
prohibitive.  However, hardware texture mapping is a firm requirement
for high-end graphics workstations.  The problem is thus to provide
hardware performance texture mapping in graphics systems while
avoiding intolerable cost and power overhead.

      The Solution - The pipeline of a Type-3 graphics adapter (one
with on-adapter geometry processing) is illustrated in Fig. 1,
although this invention is equally appropriate for Type-2 graphics
adapters (those without geometry processing subsystem 101).  In a
Type-2 graphics adapter, rasterization subsystem 102 attaches
directly to the host processor 100, and host processor 100 performs
the functions associated with geometry processing subsystem 101.
Rasterization subsystem 102 stores data into frame buffer 103, which
is comprised of both Video Random Access Memory (VRAM) and Dynamic
Random Access Memory (DRAM).  The visual data stored in frame buffer
103 is passed through RAMDAC 106 and converted into analog control
signals for monitor 107.

      Fig. 2 illustrates rasterization subsystem 102 in further
detail.  Data is received from geometry subsystem 101 (which may be
host processor 100) and passed to setup logic 201.  Setup logic 201
determines the necessary cofactors and slope information to perform
shading and interpolation of lines, triangles, or quadrilaterals.
The output of setup logic 201 is then passed to a plurality of
interpolators 203a-203z.  A system may be comprised of any number of
interpolators 203.  In the preferred embodiment 4 interpolators 203
are used, labeled 203a, 203b, 203c, and 203d.  Interpolator 203
generates the individual pixel...