Browse Prior Art Database

RS/6000 Parallel Port Architectural Verification Loader Program

IP.com Disclosure Number: IPCOM000112669D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 117K

Publishing Venue

IBM

Related People

Buckel, LL: AUTHOR [+5]

Abstract

The RS/6000 Parallel Port Architectural Verification Loader Program provides the software environment for the loading, execution, and checking of RS/6000 AVP tests. The Architectural Verification Programs (AVPs) are loaded through a standard parallel port interface.

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RS/6000 Parallel Port Architectural Verification Loader Program

      The RS/6000 Parallel Port Architectural Verification Loader
Program provides the software environment for the loading, execution,
and checking of RS/6000 AVP tests.  The Architectural Verification
Programs (AVPs) are loaded through a standard parallel port
interface.

      The RS/6000 Parallel Port Architectural Verification Loader
Program allows AVPs to be loaded into an RS/6000 through a standard
parallel port interface at high rates of speed relative to previous
approaches, invokes execution of these tests, checks the results of
the tests against predicted values provided in the AVP and returns
the results of the tests to an RT-PC* or RS/6000 host controller.
The program provides facilities for initiating asynchronous activity
during the execution of the AVPs.  By initializing asynchronous
activity such as DMA and I/O interrupts to the RS/6000 Central
Electronics Complex (CEC), additional test coverage is achieved since
additional CEC functions are utilized in handling this asynchronous
activity.

      The AVP Loader is written in C and assembly code, compiled on
an RS/6000, and loaded into the RS/6000 targeted for AVP execution
from a bootable diskette or from the Engineering Support Processor
(ESP).  The ESP is an RS/6000 development tool that allows serial
access to internal RS/6000 CEC facilities.  Software routines that
initialize the load address of the code and data are part of the AVP
loader software, making an operating system unnecessary for the
execution of this program.

      A flow chart of the AVP loader is shown in the Figure.  The
program first initializes the addresses for the program stack and
table of contents so that it can access program data and variables.
The parallel port hardware is then enabled, initialized for
bidirectional data transfers, and set up to receive data.  The
program then waits for valid receive data from the parallel port.
Each byte of the AVP is received and put into an array for decode.
AVPs consist of one or more test cases with blocks of initial and
expected values for registers, data, and instructions.  Unique
headers in the AVP identify test cases, initial and resultant
registers, data, and instructions.  These headers are decoded and
initialization data is put into the appropriate registers and memory
locations.  Expected data and registers are saved to arrays for
comparison to actual results after test-case execution.  Before
test-case execution, the AVP loader can optionally initiate interrupt
and/or DMA activity.  RS/6000 external in...