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Ceramic via Configuration

IP.com Disclosure Number: IPCOM000112670D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Kim, J: AUTHOR [+4]

Abstract

Circuit package integrity is more easily maintained by using an interconnecting via configuration for stacked ceramic layers that interlocks with each layer and distributes stress during expansion encountered in processing.

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Ceramic via Configuration

      Circuit package integrity is more easily maintained by using an
interconnecting via configuration for stacked ceramic layers that
interlocks with each layer and distributes stress during expansion
encountered in processing.

      In the Figure, individual ceramic layers 1 are fabricated with
a conical hole 2 and filled to form a conducting via 3 in multilayer
packages.  From the approximate package midpoint, the tapered holes
in individual layers are oriented in opposite directions, as shown.
This configuration accommodates expansion during temperature rise and
preserves the module stability.