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Browse Prior Art Database

Automatic Cache Line Access Monitoring

IP.com Disclosure Number: IPCOM000112672D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Van Fleet, JW: AUTHOR

Abstract

Disclosed is a hardware mechanism to provide a correctness and performance enhancement to software cache coherency maintenance. Multiprocessing computer configurations which do not implement cache coherency in hardware are cheaper and scale easier than hardware cache coherence multiprocessors. The disclosed mechanism provides information which will assist software in higher performance and correctness with less false sharing. An earlier article [*] describes the general technique of software synchronization with "lock and flush". The mechanism described herein enhances that technique. The essence of the hardware architecture is that the hardware recognizes when a cache line is retrieved from main storage and, if appropriate, the hardware sets an indicator when a cache line is retrieved.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 57% of the total text.

Automatic Cache Line Access Monitoring

      Disclosed is a hardware mechanism to provide a correctness and
performance enhancement to software cache coherency maintenance.
Multiprocessing computer configurations which do not implement cache
coherency in hardware are cheaper and scale easier than hardware
cache coherence multiprocessors.  The disclosed mechanism provides
information which will assist software in higher performance and
correctness with less false sharing.  An earlier article [*]
describes the general technique of software synchronization with
"lock and flush".  The mechanism described herein enhances that
technique.  The essence of the hardware architecture is that the
hardware recognizes when a cache line is retrieved from main storage
and, if appropriate, the hardware sets an indicator when a cache line
is retrieved.  Subsequently, software issues a new instruction which
will flush/invalidate all of the cache lines which have the indicator
set.

      The mechanism in the hardware architecture which determines
when it is appropriate to set the cache line indicator can be one of
many options:

1.  An indicator in the page frame table.

2.  A global, CPU-wide indicator in a state register.

3.  An indicator in the segment register.

The segment register indicator is probably the most convenient.  The
software will use this mechanism in the following way:

1.  A "software lock" protecting the data in question is obtained.

2.  Prior to accessing...