Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Dual-Sided Multi-Chip Electronic Package

IP.com Disclosure Number: IPCOM000112673D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Daniels, L: AUTHOR [+4]

Abstract

Dual-sided modules have been used in memory applications. This disclosure proposes a dual-sided multi-chip module package for logic (processor) applications. This innovation is facilitated by evolution both in packaging technologies and processor design. A key improvement in packaging technology is the availability of high density pinless area array connectors. The processor characteristic enabling dual-sided mounting is the more common utilization of wide interconnecting wiring buses as opposed to purely random logic interconnections on earlier designs. By placing chips requiring bussed chip-to-chip connections on opposite sides of a chip carrier, interconnections can be performed by very short vertical conductors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 63% of the total text.

Dual-Sided Multi-Chip Electronic Package

      Dual-sided modules have been used in memory applications.  This
disclosure proposes a dual-sided multi-chip module package for logic
(processor) applications.  This innovation is facilitated by
evolution both in packaging technologies and processor design.  A key
improvement in packaging technology is the availability of high
density pinless area array connectors.  The processor characteristic
enabling dual-sided mounting is the more common utilization of wide
interconnecting wiring buses as opposed to purely random logic
interconnections on earlier designs.  By placing chips requiring
bussed chip-to-chip connections on opposite sides of a chip carrier,
interconnections can be performed by very short vertical conductors.

      In general, dual-sided multi-chip packages require power and
signal Input/Output (I/O) connections to be attached only on the
periphery of the module.  This creates two problems:  One is
providing adequate signal connector area.  The second is the voltage
drop between peripherally located power connectors and centrally
located chips.  The signal connector area problem is remedied through
both higher density connectors which provide more connections in the
available space, and through a lower signal I/O demand for an
aggregate number of circuits.  Previous packages containing a system
partition of random logic had a higher per circuit I/O count than
"functional island" sub-assemblies.  ...