Browse Prior Art Database

Using Metal Lines as Source Termination for Off-Chip Drivers

IP.com Disclosure Number: IPCOM000112676D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Cao, TA: AUTHOR [+3]

Abstract

In high speed applications in the range of more than 100 Mhz, data transfers between silicon chips cause noise due to reflections, overshoot/undershoot, and ringing. This disclosure proposes a method of using metal lines as source termination for Off-Chip Drivers (OCDs).

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Using Metal Lines as Source Termination for Off-Chip Drivers

      In high speed applications in the range of more than 100 Mhz,
data transfers between silicon chips cause noise due to reflections,
overshoot/undershoot, and ringing.  This disclosure proposes a method
of using metal lines as source termination for Off-Chip Drivers
(OCDs).

      In general, it is desirable to place OCDs near C4 pads so that
the metal line resistance from OCD output to C4 is minimized.  Due to
the voltage divider effect, the signal that drives the transmission
line may lose some voltage due to resistance during a transition and
may not be able to switch a receiver at the far-end at the first
incident reflection.  This condition creates difficulties in layout
placement on the chip.
a) Each OCD has to be placed separately, as near to each C4 as
possible.  Placing them as banks may cause difficulties.
b) Some internal circuits that are close to C4s may be cut into
pieces and have to be moved away to clear the way for OCDs.

      However, sometimes OCD overdrives a transmission line.  When
OCD impedanc is smaller than transmission line impedance,
overshoot/undershoot occurs.  To make both of them equal, source
termination is used, which is usually an off-chip discrete resistor
or an on-chip BR mask resistor.  This disclosure proposes using
on-chip metal lines as source termination.

      Each OCD that needs source termination must have a certain
range of metal line length between its output and C4.  In CMOS5X, 5
layers of metal are available: M1, M2, M3, M4, and latch metal LM.
Of 5 metal layers, 3 distinct resistive co...