Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

High Performance Data Receiver

IP.com Disclosure Number: IPCOM000112691D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Katoh, Y: AUTHOR

Abstract

This article describes a high performance data receiver which is to be used as a data receiver of the pipelined data processing system and can receive the data having very little hold time. This invention, therefore, enables high frequency data receiving.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 89% of the total text.

High Performance Data Receiver

      This article describes a high performance data receiver which
is to be used as a data receiver of the pipelined data processing
system and can receive the data having very little hold time.  This
invention, therefore, enables high frequency data receiving.

      Fig. 1 shows the timing diagram, and Fig. 2 shows the block
diagram.  The transparent latches initially receive the data
(indicated by DATA0 (0..n) in both Figures and send the data to the
first edge trigger DFFs in a pipelined system.  The clock (indicated
by CLOCK) which controls these transparent latches comes earlier than
any other clocks used by the internal pipelined system, so that DATA0
(0..n) can have enough hold time without having delay lines before
the transparent latches.

      The transparent latches send data transparently when the CLOCK
is low and latch data when the CLOCK is high.  Thus, valid data
period of DATA1 (0..n), which are the outputs of the transparent
latches, is expanded in the manner shown in Fig. 1.  To minimize the
skew of the internal clocks which control each DFF of the pipelined
data processing system, the clocks are usually driven by a so-called
clock power tree.  As a result, the clock power tree causes delays
along with CLOCK_1, CLOCK_2, ..., and CLOCK_n.  The transparent
latches extend the valid data period so that the next DFF can get the
valid data having enough setup and hold the time margin even if the
clocks from th...