Browse Prior Art Database

Extendable Digital Frequency Comparator Using Standard Logic

IP.com Disclosure Number: IPCOM000112694D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Johnson, DWJ: AUTHOR

Abstract

A high resolution N-way frequency comparator using standard logic is described. Signals are paired, and the results of each individual comparison are combined.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Extendable Digital Frequency Comparator Using Standard Logic

      A high resolution N-way frequency comparator using standard
logic is described.  Signals are paired, and the results of each
individual comparison are combined.

      A high resolution circuit discriminates between signals very
close in frequency.  N signals are paired, and each pair is
individually compared.  A total of (N-1)factorial circuits is used.
Each of these individual comparisons are then fed to a monitor
circuit whose duty it is to accept all the comparisons, decide the
order of the clocks, and issue resets to the comparison circuits.
The final output should be the "best" clock, which is in the middle
of the comparisons (unless some of the clocks are dead).  If it were
desired, an ordering of frequencies, such as which is the lowest
frequency, which is the highest, and so on, would also be possible.

      For each pair, a circuit (Fig. 1) detects when either clock is
present, then either incrementing or decrementing a counter.  On each
edge of the input clocks, it forces the first stage SR high until the
second stage counts the pulse, then resets the first stage.  One
could also reset the first stage by ANDing the Q output and the
clock, if the SR inputs were edge-triggered.  It doesn't matter
whether every single input clock is counted or not.  It helps if the
common clock is higher than the two clocks it is counting.  When
either an underflow or an overflow out of the counter occurs, it is
then known for that pair which is a higher and which is the lower of
the two frequencies.

      A table is built with an entry about what to do in each
combination of comparisons (Fig. 2).  A different table would be
needed for a different value of N.  It then becomes a simple matter
of logic reduction to implement the decision and reset logic.

      As an additional condition, if any of the clocks are de...