Browse Prior Art Database

Nested Phase-Lock Loops for Board Level Clocking

IP.com Disclosure Number: IPCOM000112695D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 107K

Publishing Venue

IBM

Related People

Johnson, DWJ: AUTHOR

Abstract

Phase-Locked Loops (PLLs) can be used to eliminate clock phase errors between clocks. This is useful for reducing instruction cycle times and increasing execution speed. By nesting PLLs, clock phase errors between multiple clock boundaries can be reduced instead of only a single clock boundary.

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This is the abbreviated version, containing approximately 52% of the total text.

Nested Phase-Lock Loops for Board Level Clocking

      Phase-Locked Loops (PLLs) can be used to eliminate clock phase
errors between clocks.  This is useful for reducing instruction cycle
times and increasing execution speed.  By nesting PLLs, clock phase
errors between multiple clock boundaries can be reduced instead of
only a single clock boundary.

      The cycle time of a machine is determined by the launch time
(the time it takes for a chip to launch data once it receives the
clock), the propagation time (the travel time from one chip to
another), and the setup time (the expected arrival time relative to
the clock edge).  Because the two chips have different clocks
traveling along different paths, some difference in the clock edges
will be seen, which introduces clock skew.  This clock skew must also
be added into the actual cycle time to find the minimum achievable
cycle time for any specific transfer.

      If the output clock is fed back to the input of a PLL, the
output phase will be adjusted until the feedback and input phases
match.  So, by introducing clock distribution delay into the feedback
loop of a PLL, the delay and, more importantly, the variation is
cancelled.  Then, no matter what the path delay is, since it's in the
feedback path, the output clock will be phase adjusted to match the
input clock.

      To distribute a clock around a board to many chips, clocks must
be redriven in a buffer,  so additional skew is introduced.  On a
board level, by including clock buffers in a PLL feedback path, delay
and skew can be eliminated.  This allows chips that would have had
significant skew due to clock paths to operate at a much lower cycle
time once this skew has been eliminated.

      Inside any chip there is significant delay and therefore skew
distributing the clock to all the latches.  By including this
internal delay in an internal PLL feedback loop so that the clocks at
the latches match the input clock, the internal clock skew can be
eliminated.

      By using a PLL to cancel the board level clock driver and
distribution delays and an internal PLL to cancel internal clock
distribution delays, both exchanges on a single clock boundary and
exchanges between chips on different clock boundaries (different
boards) are aided.  The limitation is still that all chips must have
a PLL inside, or the skew between chips with a PLL (essentially zero
delay) and chips without a PLL (can be 1-5 ns) becomes large and
cancels any benefit.

      The benefits aren't too obvious.  One would think that all the
benefits of introducing the on-chip PLL were just undone.  By
cancelling the on-chip dis...